Href":"/gcse/computer-science/edexcel/questions","basePath":"/gcse/computer-science/edexcel/hardware/questions","formulaUrl":null,"initialIndex":78,"initialQuestionWindow":[{"id":"bfec2c6b-3709-4c09-8277-4e2116233d6a","revisionId":"fe1798b1-3c64-44a4-b76d-cf434dff2d6b","questionNumber":null,"questionType":"LA","specification":"","difficulty":2,"difficultyBand":"easy","totalMarks":1,"sourceTitle":null,"calculatorUse":null,"parts":[{"id":"d1a3da73-59ed-4f4f-a1f6-e632d082ec9d","label":null,"content":"Name the type of volatile main memory used to temporarily store the operating system, applications, and data currently in use.","markscheme":"- RAM (or Random Access Memory) B1","marks":1,"order":0,"markingRubric":null,"explanation":null,"options":[]}],"options":[],"explanation":null,"firstAttemptFullMarks":null},{"id":"d1494de5-a70d-459d-a5dd-73423215ec9f","revisionId":"ce648fb8-d4a6-4e40-abce-2824ebf4a07d","questionNumber":null,"questionType":"LA","specification":"An autonomous agricultural drone uses an on-board flight controller containing a Central Processing Unit (CPU) and Random Access Memory (RAM) to survey crop fields.","difficulty":4,"difficultyBand":"easy","totalMarks":2,"sourceTitle":null,"calculatorUse":null,"parts":[{"id":"5ef67e0e-7ef8-4281-a9d5-3c470e98c0f8","label":null,"content":"Explain why the drone's flight controller requires RAM while actively performing a survey flight.","markscheme":"- Identifies that RAM is used to temporarily store the active flight control software, real-time sensor readings, or mapping data currently in use. B1\n- Explains that RAM provides high-speed read/write access to the CPU, allowing instructions to be fetched and executed in real-time without the latency/bottlenecks associated with retrieving them directly from slower secondary storage (such as an SD card or flash memory). B1","marks":2,"order":0,"markingRubric":null,"explanation":null,"options":[]}],"options":[],"explanation":null,"firstAttemptFullMarks":null},{"id":"d6aef5b6-9fe4-440d-b3da-3c083ce11a7e","revisionId":"3dd094a6-514c-4d59-928f-c1fad90b52e9","questionNumber":null,"questionType":"LA","specification":"The Von Neumann architecture uses three system buses to transfer data, memory addresses, and control signals between the CPU and Main Memory.","difficulty":4,"difficultyBand":"easy","totalMarks":3,"sourceTitle":null,"calculatorUse":null,"parts":[{"id":"5bd0e855-6dfe-44e8-a6c7-2599005a0465","label":null,"content":"Complete the diagram by identifying:\n- the names of the **two** unlabeled buses, **P** and **Q**\n- the direction of the arrow at connection **R** to show the correct flow of address signals\n\n![System bus architecture diagram showing CPU on the left, Main Memory on the right, Bus P, Bus Q with connection R, and the Data Bus.](https://assets.mathsgenie.co.uk/aqa-qb/4faccf58-df6a-4f79-9f70-ba283c48e19e.png)","markscheme":"- Identifies **Bus P** as the **Control bus** B1\n- Identifies **Bus Q** as the **Address bus** B1\n- Identifies that the arrow at **Connection R** must point away from the CPU (pointing to the right / towards the Address bus) because address signals are unidirectional and originate from the CPU B1","marks":3,"order":0,"markingRubric":null,"explanation":null,"options":[]}],"options":[],"explanation":null,"firstAttemptFullMarks":null}],"subjectCode":"gcse_computer_science","summaries":[{"id":"0134bd05-2f75-4e2b-9e6b-0186e46d8c19","difficultyBand":"easy","calculatorUse":null},{"id":"069e3150-0c3f-46ae-9cd9-9f0a2dc913fc","difficultyBand":"easy","calculatorUse":null},{"id":"0708efb2-1685-431c-a3e1-e27fc0e78b69","difficultyBand":"easy","calculatorUse":null},{"id":"08223b2e-dc24-4792-8b8e-1c88f1d5ec49","difficultyBand":"easy","calculatorUse":null},{"id":"0a8f7e86-784f-495f-80bf-cbe039af3078","difficultyBand":"easy","calculatorUse":null},{"id":"13e783fd-a40c-46f0-8b6e-3cc17de6004b","difficultyBand":"medium","calculatorUse":null},{"id":"14d6b53a-8a32-4c28-b8d5-c0e064456c68","difficultyBand":"easy","calculato

Hardware

Question 47

Hardware Questions

Hardware

Question 47

Hardware Questions