Href":"/gcse/computer-science/edexcel/questions","basePath":"/gcse/computer-science/edexcel/hardware/questions","formulaUrl":null,"initialIndex":19,"initialQuestionWindow":[{"id":"244dbf83-4d2b-429f-828d-b2abdb227e82","revisionId":"62df9e78-ff8a-43f7-bb58-ddd929cc7a27","questionNumber":null,"questionType":"LA","specification":"","difficulty":3,"difficultyBand":"easy","totalMarks":1,"sourceTitle":null,"calculatorUse":null,"parts":[{"id":"7d025960-4a61-4e4f-9944-6ff073cd7aca","label":null,"content":"State one reason why a smart thermostat's startup instructions (bootstrap loader) are stored in ROM rather than RAM.","markscheme":"- ROM is non-volatile (whereas RAM is volatile), meaning it retains its data/instructions when the device is powered off, OR ROM is read-only, preventing the startup instructions from being accidentally overwritten, modified, or corrupted B1","marks":1,"order":0,"markingRubric":null,"explanation":{"methods":[{"id":"rom_startup_reason","label":"Use ROM properties","steps":[{"type":"text","order":0,"title":"Explain ROM choice","content":"The bootstrap loader must still be available when the thermostat is switched back on. **Non-volatile** means that data is kept when the power is off, so ROM retains the startup instructions whereas RAM would lose them. This earns **B1**.","highlights":[{"text":"startup instructions (bootstrap loader) are stored in ROM rather than RAM.","location":"specification"}]}]}],"generatedAt":"2026-07-21T04:50:27.612Z","modelVersion":"gpt-5.6-terra","explanationVersion":"v3"},"options":[]}],"options":[],"explanation":null,"firstAttemptFullMarks":null},{"id":"2918a733-1bbc-4c0c-932f-9e9f72e7165f","revisionId":"d10bbdc6-76f0-49cf-b06b-14079631e4c9","questionNumber":null,"questionType":"LA","specification":"In a CPU based on the von Neumann architecture, registers are used to temporarily store data and addresses.","difficulty":3,"difficultyBand":"easy","totalMarks":2,"sourceTitle":null,"calculatorUse":null,"parts":[{"id":"72167808-c285-4686-a7ec-8f2b6b26ecf9","label":null,"content":"State the **two** CPU registers that are specifically used to hold memory addresses during the Fetch-Decode-Execute cycle.","markscheme":"- Program Counter (PC) B1\n- Memory Address Register (MAR) B1","marks":2,"order":0,"markingRubric":null,"explanation":null,"options":[]}],"options":[],"explanation":null,"firstAttemptFullMarks":null},{"id":"2c2b2781-734d-4d64-bbad-b30778fc3337","revisionId":"d34f4fa9-56a0-433f-acbf-62f523dfa696","questionNumber":null,"questionType":"LA","specification":"The CPU utilizes system buses to transmit data, instructions, and control signals between the CPU, memory, and other hardware components.","difficulty":2,"difficultyBand":"easy","totalMarks":3,"sourceTitle":null,"calculatorUse":null,"parts":[{"id":"dbb2ef0a-e6d6-4cf9-910d-4df07d3793be","label":null,"content":"Complete the table by writing the correct bus (**Address Bus**, **Data Bus**, or **Control Bus**) for each role.\n\n| Bus | Role |\n| :--- | :--- |\n| | Carries physical addresses of memory locations to specify where data should be read from or written to. |\n| | Carries synchronization, command, and timing signals (such as read/write requests and interrupts) from the Control Unit. |\n| | Transports the actual data values or program instructions between the CPU registers and main memory. |","markscheme":"- Identifies **Address Bus** for the first role (carrying physical addresses) B1\n- Identifies **Control Bus** for the second role (carrying synchronization, command, and timing signals) B1\n- Identifies **Data Bus** for the third role (carrying actual data or instructions) B1","marks":3,"order":0,"markingRubric":null,"explanation":null,"options":[]}],"options":[],"explanation":null,"firstAttemptFullMarks":null}],"subjectCode":"gcse_computer_science","summaries":[{"id":"0134bd05-2f75-4e2b-9e6b-0186e46d8c19","difficultyBand":"easy","calculatorUse":null},{"id":"069e3150-0c3f-46ae-9cd9-9f0a2dc913fc","difficultyBand":"easy","cal

Hardware

Question 14

Hardware Questions

Hardware

Question 14

Hardware Questions