Href":"/gcse/computer-science/edexcel/questions","basePath":"/gcse/computer-science/edexcel/hardware/questions","formulaUrl":null,"initialIndex":52,"initialQuestionWindow":[{"id":"7c3e7a8b-2009-43bb-afae-9bc8a54488db","revisionId":"5183dff0-0681-4261-be2d-6c3d743d0fc8","questionNumber":null,"questionType":"LA","specification":"The diagram shows a simplified representation of some CPU registers and main memory during the Fetch-Decode-Execute cycle.\n\n![CPU Registers and Main Memory Interaction](https://assets.mathsgenie.co.uk/aqa-qb/f7b60293-08d1-4d89-b623-62e0b8056781.png)","difficulty":5,"difficultyBand":"easy","totalMarks":2,"sourceTitle":null,"calculatorUse":null,"parts":[{"id":"5308da72-a014-415c-9947-8800988ce131","label":null,"content":"Describe the function of the register labelled Component K.","markscheme":"- Identifies Component K as the Memory Data Register (MDR) or Memory Buffer Register (MBR) B1\n- Explains that it temporarily stores the instruction or data that has been fetched from main memory, or data that is waiting to be written to main memory B1","marks":2,"order":0,"markingRubric":null,"explanation":null,"options":[]}],"options":[],"explanation":null,"firstAttemptFullMarks":null},{"id":"82f6b3d8-0f24-40db-9a63-f13d87d7064c","revisionId":"c5401be7-ecde-4753-9b75-5715d94c8c70","questionNumber":null,"questionType":"LA","specification":"","difficulty":2,"difficultyBand":"easy","totalMarks":1,"sourceTitle":null,"calculatorUse":null,"parts":[{"id":"1f580830-b247-422c-82eb-64d335452882","label":null,"content":"State the name of the dedicated processor register within the Von Neumann architecture that holds the memory address of the next instruction to be fetched and executed.","markscheme":"- Program Counter (or PC) B1","marks":1,"order":0,"markingRubric":null,"explanation":null,"options":[]}],"options":[],"explanation":null,"firstAttemptFullMarks":null},{"id":"862812c2-3eb1-49a4-a88f-83de521fc219","revisionId":"5768f5b1-d173-4434-a15c-ff9d719768f0","questionNumber":null,"questionType":"LA","specification":"","difficulty":3,"difficultyBand":"easy","totalMarks":3,"sourceTitle":null,"calculatorUse":null,"parts":[{"id":"67085a50-76c2-411f-bbf4-7ca1d60408f2","label":null,"content":"The Von Neumann architecture relies on system buses to manage the flow of information during the Fetch-Decode-Execute (FDE) cycle.\n\nComplete the table below by writing the correct system bus (**Address Bus**, **Data Bus**, or **Control Bus**) that corresponds to each description.\n\n| Bus | Description |\n| :--- | :--- |\n| | A bidirectional pathway that transmits the machine-code instructions fetched during the FDE cycle or the operand values written to memory during the Execute phase. |\n| | A unidirectional pathway that carries binary memory addresses from the Memory Address Register (MAR) to the address decoder of the main memory. |\n| | A pathway that carries command, timing, and status signals (such as read/write lines, clock pulses, and interrupt requests) from the Control Unit to other system components. |","markscheme":"- Identifies **Data Bus** for the first role (transmitting machine-code instructions and operand values bidirectionally) B1\n- Identifies **Address Bus** for the second role (carrying binary memory addresses unidirectionally from the MAR) B1\n- Identifies **Control Bus** for the third role (carrying command, timing, and status signals from the Control Unit) B1","marks":3,"order":0,"markingRubric":null,"explanation":null,"options":[]}],"options":[],"explanation":null,"firstAttemptFullMarks":null}],"subjectCode":"gcse_computer_science","summaries":[{"id":"0134bd05-2f75-4e2b-9e6b-0186e46d8c19","difficultyBand":"easy","calculatorUse":null},{"id":"069e3150-0c3f-46ae-9cd9-9f0a2dc913fc","difficultyBand":"easy","calculatorUse":null},{"id":"0708efb2-1685-431c-a3e1-e27fc0e78b69","difficultyBand":"easy","calculatorUse":null},{"id":"08223b2e-dc24-4792-8b8e-1c88f1d5ec49","difficultyBand":"easy","calculatorUse":null},{"id":"0a8f7e86

Hardware

Question 33

Hardware Questions

Hardware

Question 33

Hardware Questions