An automated deep-sea submersible's navigation controller is executing its primary trajectory-correction algorithm. During the Fetch-Decode-Execute (FDE) cycle, a machine code instruction has just been fetched from primary memory (RAM) and loaded via the data bus. Before this instruction can be executed, it must be split into its constituent opcode and operand to determine the operation to perform.

Referring to the diagram of the Von Neumann architecture below, identify the CPU register that holds the instruction during this decoding stage, and the primary CPU component responsible for decoding the instruction.