A 4-bit binary counter has a clock input pin CK, an active-high reset pin R, and output pins Q0Q_0Q0, Q1Q_1Q1, Q2Q_2Q2, and Q3Q_3Q3, where Q0 Q_0\,Q0 is the least significant bit. State the type of 2-input logic gate and the counter outputs to which its inputs must be connected so that the circuit functions as a modulo-6 counter.
Table 1 shows how the values of the controller inputs Q2Q1Q0 Q_2 Q_1 Q_0\,Q2Q1Q0 control the logic level applied to each of the segments p p\,p to v v\,v during the counting cycle of a modulo-6 counter.
Table 1
| Logic inputs | Logic outputs | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| Q2Q_2Q2 | Q1Q_1Q1 | Q0Q_0Q0 | ppp | qqq | rrr | sss | ttt | uuu | vvv |
| 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 |
| 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 |
| 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 |
| 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 1 |
| 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
One of the logic outputs p p\,p to v v\,v is controlled by a single NOT gate connected to one of the inputs Q0Q_0Q0, Q1Q_1Q1, or Q2Q_2Q2. State the input that is used and the segment that this NOT gate controls.
X X\,X represents one of the logic outputs. The Boolean expression for this output is:
X=(Q0⋅Q1‾)+Q2 X = (Q_0 \cdot \overline{Q_1}) + Q_2 X=(Q0⋅Q1)+Q2Identify which of the logic outputs p p\,p to v v\,v is controlled by this function.
Y Y\,Y represents another of the logic outputs. The Boolean expression for this output is:
Y=(Q0⋅Q1‾)‾+(Q1‾⋅Q2‾) Y = \overline{(Q_0 \cdot \overline{Q_1})} + (\overline{Q_1} \cdot \overline{Q_2}) Y=(Q0⋅Q1)+(Q1⋅Q2)Explain the configuration of logic gates (NOT, AND, NAND, OR) needed to construct a circuit representing this expression, tracing the signal path from inputs Q0Q_0Q0, Q1Q_1Q1, and Q2 Q_2\,Q2 to output YYY.