Skip to content
MathsGenie logo
Open app

Course home

  1. A Level
  2. Physics AQA
  3. Revision guides

Astables (A-level only)

Digital circuits are incredibly fast, but they need a "heartbeat" to keep all their components synchronised. If different parts of a computer system try to process data at slightly different times, the entire system crashes. This heartbeat is provided by a specific type of circuit called an astable.

What you'll learn:

  • What an astable oscillator is and why digital systems need clock pulses.
  • The anatomy of a clock pulse, including period, frequency, and pulse width.
  • How to calculate the duty cycle and mark-to-space ratio of a signal.
  • How to change the frequency of an astable using an external resistor-capacitor (RCRCRC) network.

What is an Astable?

Imagine trying to row a boat with eight people. Without a coxswain shouting "stroke... stroke...", everyone would row at their own pace, and the boat would go nowhere. In digital electronics, the "coxswain" is the astable.

Definition

Astable

An astable is a type of oscillator circuit that has no stable states. It continuously and automatically switches back and forth between a logic 1 (HIGH voltage) and a logic 0 (LOW voltage) without needing any external trigger.

Because it oscillates constantly, the output of an astable provides a continuous stream of square-wave voltage pulses. We call this stream a clock pulse. Every time the clock pulse ticks, the digital circuit moves to its next task.


The Anatomy of a Clock Pulse

To analyse an astable, we need to be able to describe the square wave it produces. We use a few very specific terms to map out the timing of the pulse.

Digital square wave diagram showing Mark, Space, and Period

Definition

Clock pulse timings

  • Mark (tONt_{\text{ON}}tON​): The time the signal spends in the HIGH (logic 1) state. This is also called the pulse width.
  • Space (tOFFt_{\text{OFF}}tOFF​): The time the signal spends in the LOW (logic 0) state.
  • Period (TTT): The total time taken for one complete cycle. It is the sum of the mark and the space: T=tON+tOFFT = t_{\text{ON}} + t_{\text{OFF}}T=tON​+tOFF​.
  • Clock rate / Frequency (fff): The number of complete clock pulses per second, measured in hertz (Hz).

Just like in standard wave mechanics, the relationship between frequency and period is:

f=1T f = \frac{1}{T} f=T1​

Duty Cycle and Mark-to-Space Ratio

Engineers don't just care about how fast the clock is ticking; they also care about the shape of the pulse. A clock pulse doesn't have to be perfectly symmetrical (spending exactly half its time ON and half its time OFF).

We measure this shape in two different ways:

  1. Duty Cycle: This is the percentage of the total period that the signal is HIGH.
Duty Cycle=(tONT)×100% \text{Duty Cycle} = \left( \frac{t_{\text{ON}}}{T} \right) \times 100\% Duty Cycle=(TtON​​)×100%
  1. Mark-to-Space Ratio: This is the direct ratio of the time spent HIGH compared to the time spent LOW.
Mark-to-Space Ratio=tONtOFF \text{Mark-to-Space Ratio} = \frac{t_{\text{ON}}}{t_{\text{OFF}}} Mark-to-Space Ratio=tOFF​tON​​
Common Mistake

Ratios vs Percentages

Students frequently confuse duty cycle with mark-to-space ratio.

  • Duty Cycle compares the mark to the whole cycle (TTT).
  • Mark-to-Space compares the mark to the space (tOFFt_{\text{OFF}}tOFF​). If a signal is ON for 2 ms2\text{ ms}2 ms and OFF for 3 ms3\text{ ms}3 ms, the mark-to-space ratio is 2:32:32:3, but the duty cycle is 2/5=40%2/5 = 40\%2/5=40%.
Example

Calculating clock pulse characteristics

An astable oscillator produces a clock pulse with a frequency of 5.0 kHz5.0\text{ kHz}5.0 kHz. The mark-to-space ratio is 1:31:31:3. Calculate the pulse width and the duty cycle of the signal.

  1. First, find the total period (TTT) of one cycle using the frequency.
T=1fT=15000T=2.0×10−4 s=200 \mus \begin{aligned} T &= \frac{1}{f} \\ T &= \frac{1}{5000} \\ T &= 2.0 \times 10^{-4}\text{ s} = 200\text{ \mu s} \end{aligned} TTT​=f1​=50001​=2.0×10−4 s=200 \mus​
  1. Use the mark-to-space ratio (1:31:31:3) to find the fraction of the total time spent in the mark (ON) state. The ratio has a total of 1+3=41 + 3 = 41+3=4 parts. The pulse width (tONt_{\text{ON}}tON​) is 1 part out of 4.
tON=14×TtON=14×200 \mustON=50 \mus \begin{aligned} t_{\text{ON}} &= \frac{1}{4} \times T \\ t_{\text{ON}} &= \frac{1}{4} \times 200\text{ \mu s} \\ t_{\text{ON}} &= 50\text{ \mu s} \end{aligned} tON​tON​tON​​=41​×T=41​×200 \mus=50 \mus​
  1. Calculate the duty cycle using the ratio of tONt_{\text{ON}}tON​ to TTT. Since we know it's 1 part out of 4 total parts, this is straightforward:
Duty Cycle=(50200)×100%Duty Cycle=25% \begin{aligned} \text{Duty Cycle} &= \left( \frac{50}{200} \right) \times 100\% \\ \text{Duty Cycle} &= 25\% \end{aligned} Duty CycleDuty Cycle​=(20050​)×100%=25%​

Controlling the Frequency with an RC Network

If you are designing a digital circuit, you will need to choose how fast the clock runs. The astable itself is just a switching mechanism; to control when it switches, we connect an external resistor-capacitor (RCRCRC) network.

Astable block diagram with external RC network

Inside the astable, the circuit monitors the voltage across the external capacitor.

  • The capacitor charges up through the resistor until it hits a certain upper threshold voltage, causing the astable to switch its output to LOW.
  • The capacitor then discharges until it hits a lower threshold voltage, causing the astable to switch its output back to HIGH.

Because the charging and discharging times depend entirely on the time constant (τ=RC\tau = RCτ=RC), changing the value of the external resistor or capacitor changes the frequency of the clock pulse.

Key Idea

Frequency and RC values

The period (TTT) of an astable oscillator is directly proportional to the product of the external resistance and capacitance:

T∝RC T \propto RC T∝RC

Consequently, the frequency (fff) is inversely proportional to RCRCRC:

f∝1RC f \propto \frac{1}{RC} f∝RC1​

Increasing the resistance or the capacitance increases the time it takes to charge/discharge, which lengthens the period and lowers the frequency.

Tip

Don't panic about the 555 timer

You might see older textbooks or practical guides talking heavily about the internal workings of the "555 timer chip" (a very famous astable IC). You do not need to know this. The AQA specification explicitly states that knowledge of a particular circuit or specific device like the 555 chip is not required. You only need to know that an external RCRCRC network controls the frequency!

Example

Varying the RC network

An astable circuit with an external capacitance of 1.0 \muF1.0\text{ \mu F}1.0 \muF and an external resistance of 22 kΩ22\text{ k}\Omega22 kΩ produces a clock rate of 60 Hz60\text{ Hz}60 Hz. The resistor is swapped out for a 33 kΩ33\text{ k}\Omega33 kΩ resistor. Assuming the internal thresholds of the astable remain identical, what is the new clock rate?

  1. State the proportional relationship between frequency and the RCRCRC values.
f∝1RC f \propto \frac{1}{RC} f∝RC1​
  1. Set up a ratio to compare the new frequency (f2f_2f2​) to the old frequency (f1f_1f1​). Since CCC remains constant, it cancels out of the ratio.
f2f1=R1R2f2=f1×(R1R2) \begin{aligned} \frac{f_2}{f_1} &= \frac{R_1}{R_2} \\ f_2 &= f_1 \times \left( \frac{R_1}{R_2} \right) \end{aligned} f1​f2​​f2​​=R2​R1​​=f1​×(R2​R1​​)​
  1. Substitute the given values to find the new frequency.
f2=60×(22×10333×103)f2=60×(23)f2=40 Hz \begin{aligned} f_2 &= 60 \times \left( \frac{22 \times 10^3}{33 \times 10^3} \right) \\ f_2 &= 60 \times \left( \frac{2}{3} \right) \\ f_2 &= 40\text{ Hz} \end{aligned} f2​f2​f2​​=60×(33×10322×103​)=60×(32​)=40 Hz​

Exam technique

In the exam

  1. Watch out for micro and milli: Pulse widths are almost always tiny. Expect values in milliseconds (ms\text{ms}ms, 10−310^{-3}10−3) and microseconds (\mus\text{\mu s}\mus, 10−610^{-6}10−6). Always convert to standard SI seconds (s\text{s}s) before doing f=1/Tf = 1/Tf=1/T calculations.
  2. Read the graph carefully: If given an oscilloscope trace, ensure you identify whether the horizontal axis gives the period or just the mark/pulse width. Don't just grab the first number you see to calculate frequency.
  3. Proportionality is your friend: For RCRCRC network questions, you rarely need a complex formula. If resistance doubles, the period doubles, so the frequency halves. Use simple ratio mathematics (as shown in the second example) to save time.
Self review

Check yourself

  • Can you define the difference between the "mark" and the "space" of a clock pulse?
  • If a square wave has a duty cycle of 50%50\%50%, what is its mark-to-space ratio?
  • If you wanted to make a clock pulse tick faster (higher frequency), what two changes could you make to the external RCRCRC network?
PreviousNext

How was this guide?

Teach Genie

Review Astables (A-level only) by teaching Genie

Teach it back in your own words, spot gaps, and remember it better.

Start teaching
Genie and Baby Genie

Lesson

Recap your knowledge with an interactive lesson

7 minute activity

Start lesson

Square-wave clock pulse on voltage-time axes with HIGH and LOW levels, mark, space, and period labelled

An astable is an oscillator with no stable states, so it keeps switching its output between logic 1 and logic 0 without any external trigger. The result is a repeating square-wave signal called a clock pulse.

Digital circuits need these pulses to stay synchronised. Each pulse acts like a timing instruction that tells the system when to move on to the next operation.

Flashcards

Remember key concepts with flashcards

24 flashcards

Practice flashcards

What is an astable oscillator?

Astables (A-level only) Revision Guide

  1. A Level
  2. /Physics
  3. /Astables (A-level only)