e/computer-science/aqa/questions","basePath":"/gcse/computer-science/aqa/systems-architecture/questions","formulaUrl":null,"initialIndex":28,"initialQuestionWindow":[{"id":"9c8a293e-201c-4e8b-bb52-61e35d1a04e7","revisionId":"7fe5142c-71a3-4016-b6fb-9a883e51b9cf","questionNumber":null,"questionType":"LA","specification":"**Figure 1** shows a cyclic diagram representing the main stages of the CPU instruction cycle.\n\n![A sequential CPU cycle diagram showing three blocks in a loop: Block 1 is labeled 'Fetch', Block 2 is labeled with a question mark '?', and Block 3 is labeled 'Execute'. Arrows connect 'Fetch' to '?', '?' to 'Execute', and 'Execute' back to 'Fetch'.](https://assets.mathsgenie.co.uk/aqa-qb/8cd07555-3963-49c7-b636-cb0d3e176ba5.png)","difficulty":2,"difficultyBand":"easy","totalMarks":1,"sourceTitle":null,"calculatorUse":null,"parts":[{"id":"7f52d6d8-dbb0-4e9c-824b-fbcc24de6ff9","label":null,"content":"State the name of the missing stage represented by the question mark (**?**) in **Figure 1**.","markscheme":"- Identifies the missing stage as **Decode** (or **Decoding**) B1","marks":1,"order":0,"markingRubric":null,"explanation":null,"options":[]}],"options":[],"explanation":null,"firstAttemptFullMarks":null},{"id":"a4cf363f-0809-482b-8ca1-12a44c137eac","revisionId":"46d87f87-3cb3-49f3-a0f4-b913ad6253be","questionNumber":null,"questionType":"LA","specification":"","difficulty":3,"difficultyBand":"easy","totalMarks":2,"sourceTitle":null,"calculatorUse":null,"parts":[{"id":"68f6e2e9-89af-49c0-9d16-886ba2a4e5d8","label":null,"content":"Explain the role of the Program Counter (PC) during the **fetch** stage of the Fetch-Decode-Execute cycle.","markscheme":"- The Program Counter (PC) stores/holds the memory address of the next instruction to be fetched. B1\n- At the start of the fetch cycle, this address is copied/transferred to the Memory Address Register (MAR) (and the PC is then incremented to point to the next sequential instruction). B1","marks":2,"order":0,"markingRubric":null,"explanation":null,"options":[]}],"options":[],"explanation":null,"firstAttemptFullMarks":null},{"id":"afc3e652-a819-4b07-8633-8b71be1f6251","revisionId":"66213272-9762-453e-985f-b1508173c4b2","questionNumber":null,"questionType":"LA","specification":"","difficulty":3,"difficultyBand":"easy","totalMarks":3,"sourceTitle":null,"calculatorUse":null,"parts":[{"id":"5d574c83-06db-4b30-a396-ceab41c6091d","label":null,"content":"Select **three** options to show which of the following are core registers or control/execution units located inside a standard CPU based on the Von Neumann architecture.\n\n* A: Memory Address Register (MAR)\n* B: Random Access Memory (RAM)\n* C: Control Unit (CU)\n* D: Hard Disk Drive (HDD)\n* E: Current Instruction Register (CIR)\n* F: Universal Serial Bus (USB) Controller\n* G: Device Driver\n* H: Read-Only Memory (ROM)","markscheme":"- Selects **A: Memory Address Register (MAR)** (Correct - it is an internal CPU register that holds the physical memory address of the next instruction or data word to be read from or written to) B1\n- Selects **C: Control Unit (CU)** (Correct - it is a core internal component of the CPU that directs the operation of the processor, managing the fetch-decode-execute cycle) B1\n- Selects **E: Current Instruction Register (CIR)** (Correct - it is an internal CPU register that stores the instruction currently being decoded and executed) B1","marks":3,"order":0,"markingRubric":null,"explanation":null,"options":[]}],"options":[],"explanation":null,"firstAttemptFullMarks":null}],"subjectCode":"gcse_computer_science__aqa","summaries":[{"id":"04c1e9b2-cf68-4c19-82a1-523290b4fd3b","difficultyBand":"easy","calculatorUse":null},{"id":"08c607e9-617a-4765-a4c0-c1135e9732ef","difficultyBand":"medium","calculatorUse":null},{"id":"092ac1ef-7775-4ee2-a5d3-f7f3531fe4f2","difficultyBand":"hard","calculatorUse":null},{"id":"0ee69e95-ff2f-49ee-9af4-7667c0e01b3a","difficultyBand":"easy","calculatorUse":null},{"id":"134

Systems architecture

Question 15

Systems architecture Questions

Systems architecture

Question 15

Systems architecture Questions