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CPU to run a program step by step."},{"text":"It stores, processes and outputs data.","correct":false,"explanation":"This describes processing data, not the complete instruction cycle. The CPU must fetch an instruction from memory, decode it, and then execute it before moving to the next instruction."},{"text":"It inputs, processes and outputs information.","correct":false,"explanation":"Input and output are parts of a computer system, but they do not describe how the CPU runs instructions. The required cycle is fetch, decode and execute."},{"text":"It loads, translates and saves instructions.","correct":false,"explanation":"Loading, translating and saving do not identify the CPU’s repeated instruction cycle. Instructions are fetched, decoded to determine the operation, and executed by the processor."}]},{"id":"5aa4d1c8-942f-4ba9-8043-f87253b19e75","cardType":"cloze","points":null,"front":"A program is a set of [ ]; an instruction is a single [ ] for the CPU.","back":"A program is a set of instructions; an instruction is a single command for the CPU.","mcqOptions":[{"text":"A program is a set of instructions; an instruction is a single command for the CPU.","correct":true,"explanation":"A program contains multiple instructions, while an instruction is one command that tells the CPU what operation to perform. The completed sentence uses both terms accurately."},{"text":"A program is a set of values; an instruction is a single location for the CPU.","correct":false,"explanation":"A program is made from instructions, not individual data values, and an instruction is a command rather than a memory location. Confusing data with instructions reverses their roles."},{"text":"A program is a set of addresses; an instruction is a single program for the CPU.","correct":false,"explanation":"A program is not a set of addresses, although instructions may be stored at addressed locations. An instruction is a command for the CPU, not a complete program."},{"text":"A program is a set of commands; an instruction is a single instruction for the CPU.","correct":false,"explanation":"A program consists of instructions, not commands as its stored components, while an instruction is the command itself. This option swaps the relationship between the two terms."}]},{"id":"3c26129c-69aa-434b-bd39-e208df0b2b63","cardType":"cloze","points":null,"front":"For running programs in GCSE Computer Science, main memory usually means [ ].","back":"For running programs in GCSE Computer Science, main memory usually means RAM.","mcqOptions":[{"text":"RAM","correct":true,"explanation":"RAM is the volatile main memory used to hold programs and data currently needed by the CPU. Its contents are lost when power is removed."},{"text":"ROM","correct":false,"explanation":"ROM is non-volatile memory that usually stores fixed instructions such as boot firmware. GCSE questions about main memory used while programs run generally mean RAM."},{"text":"cache memory","correct":false,"explanation":"Cache memory is a small, very fast memory close to the CPU, but it is not usually what GCSE questions mean by main memory. The expected term is RAM."},{"text":"secondary storage","correct":false,"explanation":"Secondary storage holds files persistently, whereas running programs are normally loaded into volatile main memory. In this context, main memory refers to RAM."}]},{"id":"4e0367d9-0adb-4137-b6e8-f013c5099ef1","cardType":"basic","points":1,"front":"What memory arrangement distinguishes von Neumann architecture?","back":"Instructions and data share the same main memory.","mcqOptions":[{"text":"Instructions and data share the same main memory.","correct":true,"explanation":"Von Neumann architecture stores both instructions and data in the same main memory. The CPU accesses them through the shared memory system."},{"text":"Instructions and data use separate main memories.","correct":false,"explanation":"Separate memories for instructions and data describe a Harvard-style arrangement. Von Neumann architecture uses one shared main memory for both."},{"text":"Instructions are stored inside the CPU only.","correct":false,"explanation":"The CPU does not keep all instructions permanently inside its hardware in von Neumann architecture. Instructions are stored in the same main memory as data."},{"text":"Instructions and data remain only on secondary storage.","correct":false,"explanation":"External storage may hold programs and data, but it is not the defining memory arrangement of von Neumann architecture. Both are held in shared main memory during operation."}]},{"id":"fd95b6ed-4d68-4e2a-9de7-81828e2dd9e1","cardType":"basic","points":2,"front":"Why is von Neumann architecture called a stored-program design?","back":"The program is stored in memory, not built into hardware.","mcqOptions":[{"text":"The program is stored in memory, not built into hardware.","correct":true,"explanation":"It is called stored-program design because the program’s instructions are held in memory and can be changed, rather than being permanently wired into the hardware."},{"text":"The program is built into hardware, not stored in memory.","correct":false,"explanation":"Instructions being built into hardware would describe a fixed-function system, not a stored-program design. In von Neumann architecture, the program is stored in memory."},{"text":"The program is executed by the CPU, not stored in memory.","correct":false,"explanation":"The CPU executes instructions, but execution is not what makes the design stored-program. The defining feature is that the program itself is held in memory."},{"text":"The program is stored on secondary storage, not built into hardware.","correct":false,"explanation":"Secondary storage can contain programs, but the stored-program concept refers to instructions being stored in memory for the CPU to access, rather than being built into hardware."}]},{"id":"63d3d4ff-2f11-49ae-9fe1-a7a713557782","cardType":"cloze","points":null,"front":"A memory address identifies a [ ] in memory; data is a [ ] being stored, moved or processed.","back":"A memory address identifies a location in memory; data is a value being stored, moved or processed.","mcqOptions":[{"text":"A memory address identifies a location in memory; data is a value being stored, moved or processed.","correct":true,"explanation":"An address identifies where a memory item is located, while data is the value held or handled at that location. Keeping these concepts separate is essential when describing memory."},{"text":"A memory address identifies a value in memory; data is a location being stored, moved or processed.","correct":false,"explanation":"An address identifies a location, not the value stored there. Data is the value being stored or processed, so this option reverses the meanings of address and value."},{"text":"A memory address identifies an instruction in memory; data is a location being stored, moved or processed.","correct":false,"explanation":"An address is not the instruction itself, although an instruction can be stored at an address. Data is a value, not an instruction in every situation."},{"text":"A memory address identifies a command in memory; data is an instruction being stored, moved or processed.","correct":false,"explanation":"A memory address identifies a location rather than a command. Data can include instructions or other values, but the general term needed here is value."}]},{"id":"e011f391-c0bd-4dbe-aad4-707eb0eafd69","cardType":"basic","points":1,"front":"Which CPU component coordinates the fetch-decode-execute cycle?","back":"The Control Unit (CU).","mcqOptions":[{"text":"The Control Unit (CU).","correct":true,"explanation":"The Control Unit manages the fetch-decode-execute cycle by interpreting instructions and coordinating the actions of the ALU, registers, and memory."},{"text":"The Arithmetic Logic Unit (ALU).","correct":false,"explanation":"The ALU performs arithmetic and logical operations, but it does not coordinate the whole instruction cycle. The Control Unit directs the CPU’s other components."},{"text":"The registers.","correct":false,"explanation":"Registers temporarily hold data, instructions, or addresses, but they do not control the sequence of CPU operations. That coordination is performed by the Control Unit."},{"text":"The system clock.","correct":false,"explanation":"The system clock provides timing signals, but it does not interpret instructions or coordinate the CPU’s components. The Control Unit performs that coordinating role."}]},{"id":"96cd4e95-cee7-4b65-a334-46ebe6a7b1e7","cardType":"basic","points":1,"front":"How does the Control Unit direct other CPU parts and memory?","back":"It sends control signals.","mcqOptions":[{"text":"It sends control signals.","correct":true,"explanation":"The Control Unit sends control signals to coordinate the timing and actions of the ALU, registers, memory, and other CPU components."},{"text":"It sends data signals.","correct":false,"explanation":"Data signals carry values, but they do not tell components which operations to perform. The Control Unit directs the CPU using control signals."},{"text":"It sends memory addresses.","correct":false,"explanation":"Memory addresses identify locations to access, but they do not coordinate the behaviour of CPU components. Control signals provide those instructions and timing cues."},{"text":"It sends program instructions.","correct":false,"explanation":"Instructions are fetched and decoded by the CPU, rather than being the signals used to direct every component. The Control Unit sends control signals for coordination."}]},{"id":"4a92f4a8-f8bd-4ac8-8229-74556a64420c","cardType":"basic","points":1,"front":"Which component carries out arithmetic calculations such as addition?","back":"The Arithmetic Logic Unit (ALU).","mcqOptions":[{"text":"The Arithmetic Logic Unit (ALU).","correct":true,"explanation":"The ALU performs arithmetic calculations such as addition, subtraction, multiplication and division, as well as logical comparisons."},{"text":"The Control Unit (CU).","correct":false,"explanation":"The Control Unit coordinates and controls instruction execution, but it does not carry out arithmetic calculations. Addition is performed by the Arithmetic Logic Unit (ALU)."},{"text":"The Program Counter (PC).","correct":false,"explanation":"The Program Counter stores the address of the next instruction, rather than performing calculations. Arithmetic such as addition is carried out by the Arithmetic Logic Unit (ALU)."},{"text":"The Memory Address Register (MAR).","correct":false,"explanation":"The Memory Address Register stores the address of the memory location being accessed. It does not calculate values; arithmetic calculations are performed by the Arithmetic Logic Unit (ALU)."}]},{"id":"c703ca21-b931-4986-968b-75747a4a9c75","cardType":"basic","points":1,"front":"What type of ALU operation checks whether one value is greater than another?","back":"A logical operation.","mcqOptions":[{"text":"A logical operation.","correct":true,"explanation":"Comparing whether one value is greater than another is a logical operation because it tests a relationship and produces a true or false result."},{"text":"An arithmetic operation.","correct":false,"explanation":"Arithmetic operations calculate numerical results such as sums or differences. Testing whether one value is greater than another is a logical operation because it produces a true or false result."},{"text":"A loading operation.","correct":false,"explanation":"Loading transfers data into a register and does not compare values. Checking whether one value is greater than another is a logical operation performed by the ALU."},{"text":"A branching operation.","correct":false,"explanation":"Branching changes the sequence of instructions, often after a condition is tested. The comparison itself, such as checking which value is greater, is a logical operation."}]},{"id":"bdb73c91-4442-420d-82ca-a439f7e51fb0","cardType":"basic","points":2,"front":"Why can cache make the CPU work more efficiently?","back":"It gives faster access to likely-needed data and instructions.","mcqOptions":[{"text":"It gives faster access to likely-needed data and instructions.","correct":true,"explanation":"Cache is faster than RAM and stores frequently or recently used data and instructions, reducing the time the CPU waits for likely-needed information."},{"text":"It gives larger capacity for all data and instructions.","correct":false,"explanation":"Cache improves speed rather than providing larger capacity; it is usually much smaller than RAM. Faster access to likely-needed data and instructions makes the CPU more efficient."},{"text":"It gives permanent storage for data and instructions.","correct":false,"explanation":"Cache is volatile temporary memory, so it does not permanently store data or instructions. Its benefit is faster access to likely-needed information while the CPU is working."},{"text":"It gives wireless access to data and instructions.","correct":false,"explanation":"Cache is a small, fast memory located close to or within the CPU, not a wireless connection. It improves efficiency through faster access to likely-needed data and instructions."}]},{"id":"202d2fc8-6f01-4845-9695-536f009345c4","cardType":"cloze","points":null,"front":"Cache is [ ] and [ ] than RAM.","back":"Cache is smaller and faster than RAM.","mcqOptions":[{"text":"Cache is smaller and faster than RAM.","correct":true,"explanation":"Cache has a smaller capacity than RAM but can be accessed more quickly, so it stores frequently or recently used data and instructions close to the CPU."},{"text":"Cache is larger and faster than RAM.","correct":false,"explanation":"Cache is faster but not larger than RAM. Its high speed comes with limited capacity, so the correct comparison is that cache is smaller and faster than RAM."},{"text":"Cache is smaller and slower than RAM.","correct":false,"explanation":"Cache is smaller than RAM, but it is faster, not slower. Its purpose is to give the CPU rapid access to frequently or recently used information."},{"text":"Cache is larger and slower than RAM.","correct":false,"explanation":"Both comparisons are reversed here. Cache has a smaller capacity than RAM but operates faster, allowing the CPU to access likely-needed data and instructions quickly."}]},{"id":"fb8ed9d8-bcc7-43de-ae98-75b1b9abc67f","cardType":"basic","points":2,"front":"Why are registers used while the CPU carries out an instruction?","back":"They provide tiny, high-speed temporary storage.","mcqOptions":[{"text":"They provide tiny, high-speed temporary storage.","correct":true,"explanation":"Registers are very small, very fast storage locations inside the CPU. They temporarily hold data, instructions or addresses while an instruction is being processed."},{"text":"They provide large, low-speed permanent storage.","correct":false,"explanation":"Registers are tiny and volatile, not large or permanent. They provide high-speed temporary storage inside the CPU while instructions are being carried out."},{"text":"They provide wireless, high-speed communication.","correct":false,"explanation":"Registers store values inside the CPU and do not provide wireless communication. Their role is to offer tiny, high-speed temporary storage during instruction execution."},{"text":"They provide external, high-capacity storage.","correct":false,"explanation":"Registers are located inside the CPU and have extremely limited capacity. They provide tiny, high-speed temporary storage rather than external storage for large amounts of data."}]},{"id":"5547bd66-9ddd-41f5-a44a-ad4e63f002bc","cardType":"basic","points":1,"front":"A CPU is about to access memory location 104. Which register should hold 104?","back":"The Memory Address Register (MAR).","mcqOptions":[{"text":"The Memory Address Register (MAR).","correct":true,"explanation":"The MAR stores the address of the memory location that the CPU is about to access, so it would hold the value 104 in this example."},{"text":"The Memory Data Register (MDR).","correct":false,"explanation":"The MDR temporarily stores data being transferred to or from memory. The address 104 belongs in the Memory Address Register (MAR), which identifies the location to access."},{"text":"The Program Counter (PC).","correct":false,"explanation":"The Program Counter stores the address of the next instruction to fetch, not an arbitrary memory address currently being accessed. Location 104 should be held in the MAR."},{"text":"The Current Instruction Register (CIR).","correct":false,"explanation":"The Current Instruction Register holds the instruction currently being decoded or executed. A memory location address such as 104 is held in the Memory Address Register (MAR)."}]},{"id":"8ac278a4-5db7-4126-8003-efb4638a051f","cardType":"basic","points":1,"front":"An instruction has just been transferred from memory. Which register can hold it temporarily?","back":"The Memory Data Register (MDR).","mcqOptions":[{"text":"The Memory Data Register (MDR).","correct":true,"explanation":"The MDR temporarily holds data or an instruction transferred between the CPU and memory, so it can hold the instruction immediately after it has been fetched."},{"text":"The Memory Address Register (MAR).","correct":false,"explanation":"The MAR stores the address of the memory location being accessed, not the instruction transferred from it. The fetched instruction can be held temporarily in the MDR."},{"text":"The Program Counter (PC).","correct":false,"explanation":"The PC stores the address of the next instruction to fetch, rather than the instruction itself. A transferred instruction can be held temporarily in the MDR."},{"text":"The Accumulator (ACC).","correct":false,"explanation":"The Accumulator stores intermediate results from calculations and processing. An instruction transferred from memory is temporarily held in the Memory Data Register (MDR)."}]},{"id":"9a7eb0e8-f3ce-4d2d-9808-feae4ced2ee0","cardType":"basic","points":1,"front":"Which register stores the address of the next instruction to fetch?","back":"The Program Counter (PC).","mcqOptions":[{"text":"The Program Counter (PC).","correct":true,"explanation":"The Program Counter stores the address of the next instruction to be fetched, allowing the CPU to follow the correct sequence of instructions."},{"text":"The Memory Address Register (MAR).","correct":false,"explanation":"The MAR holds the address currently being accessed in memory, while the Program Counter specifically stores the address of the next instruction to fetch."},{"text":"The Memory Data Register (MDR).","correct":false,"explanation":"The MDR temporarily stores data or instructions transferred between memory and the CPU. The address of the next instruction is stored in the Program Counter (PC)."},{"text":"The Current Instruction Register (CIR).","correct":false,"explanation":"The CIR holds the instruction currently being decoded or executed. The address of the next instruction to fetch is stored in the Program Counter (PC)."}]},{"id":"35bbd8f1-de8f-43d9-93cd-b8ebb7d5441f","cardType":"cloze","points":null,"front":"After an instruction is fetched, the Program Counter is normally [ ] to point to the [ ].","back":"After an instruction is fetched, the Program Counter is normally updated to point to the next instruction.","mcqOptions":[{"text":"After an instruction is fetched, the Program Counter is normally updated to point to the next instruction.","correct":true,"explanation":"The Program Counter is updated after fetching so it contains the address of the next instruction in sequence, ready for the following fetch cycle."},{"text":"After an instruction is fetched, the Program Counter is normally updated to point to the previous instruction.","correct":false,"explanation":"The Program Counter moves forwards through the program, not backwards. After fetching, it is updated to point to the next instruction unless a jump or branch changes the sequence."},{"text":"After an instruction is fetched, the Program Counter is normally reset to point to the next instruction.","correct":false,"explanation":"Resetting would return the counter to a fixed starting value rather than advancing through the program. The correct operation is updating the Program Counter to the next instruction."},{"text":"After an instruction is fetched, the Program Counter is normally incremented to point to the current instruction.","correct":false,"explanation":"Incrementing usually advances the address, but the fetched instruction is the current one, so the counter must point to the next instruction, not remain on the current instruction."}]},{"id":"f83f5608-e2e0-484e-813c-cdbbd7354b27","cardType":"basic","points":1,"front":"The ALU has produced a calculation result needed by the next instruction. Where can it be held?","back":"In the Accumulator (ACC).","mcqOptions":[{"text":"In the Accumulator (ACC).","correct":true,"explanation":"The Accumulator is a CPU register used to hold intermediate and final results produced by the ALU, especially when a later instruction needs the value."},{"text":"In the Memory Data Register (MDR).","correct":false,"explanation":"The MDR temporarily holds data being transferred to or from memory. An ALU result needed by the next instruction is normally held in the Accumulator (ACC)."},{"text":"In the Current Instruction Register (CIR).","correct":false,"explanation":"The CIR stores the instruction currently being decoded or executed, not an arithmetic result. The Accumulator (ACC) holds calculation results needed by later instructions."},{"text":"In the Program Counter (PC).","correct":false,"explanation":"The PC stores the address of the next instruction, so confusing it with a result register mixes up control information and data. The result belongs in the Accumulator (ACC)."}]},{"id":"a290c14b-dfca-42cd-97f9-681bc0e977ab","cardType":"basic","points":1,"front":"During the fetch stage, what does the CPU get from memory?","back":"The next instruction.","mcqOptions":[{"text":"The next instruction.","correct":true,"explanation":"During the fetch stage, the CPU uses the Program Counter to locate and retrieve the next instruction from memory before placing it in the instruction register."},{"text":"The current instruction.","correct":false,"explanation":"The instruction being executed is often called the current instruction, but fetching retrieves the next instruction identified by the Program Counter before execution begins."},{"text":"The address of the next instruction.","correct":false,"explanation":"The address is supplied by the Program Counter and used to locate the instruction. Memory returns the next instruction itself, not just its address."},{"text":"The result of the previous instruction.","correct":false,"explanation":"A previous result may be stored in a register or memory, but the fetch stage retrieves an instruction from the address in the Program Counter."}]},{"id":"04b4ecd9-851e-40f0-9d18-02751e52d97c","cardType":"cloze","points":null,"front":"During decode, the CU [ ]; during execute, the instruction is [ ].","back":"During decode, the CU interprets the instruction; during execute, the instruction is carried out.","mcqOptions":[{"text":"During decode, the CU interprets the instruction; during execute, the instruction is carried out.","correct":true,"explanation":"During decode, the Control Unit interprets the opcode and operands to determine the required operation. During execute, the CPU performs that operation."},{"text":"During decode, the CU fetches the instruction; during execute, the instruction is carried out.","correct":false,"explanation":"Fetching happens before decoding and retrieves the instruction from memory. Decode interprets the instruction, while execute carries out the required operation."},{"text":"During decode, the CU interprets the instruction; during execute, the instruction is stored.","correct":false,"explanation":"Decoding correctly identifies the instruction, but execution performs it rather than simply storing it. Storage is handled by registers or memory when required."},{"text":"During decode, the CU executes the instruction; during execute, the instruction is interpreted.","correct":false,"explanation":"This reverses the decode and execute stages. The CU interprets the instruction during decode, then the instruction is carried out during execute."}]}]}],"examCountdown":{"examDate":"2027-05-10","paperLabel":"Paper 1"},"heading":"Architecture of the CPU","title":"Architecture of the CPU Flashcards","topbar":{"backHref":"/gcse/computer-science/ocr/flashcards"},"topicSidebar":"$L37"}]}],"topicId":"98045c5e-8bb9-5ecc-a849-bb5057b2dd26","walled":"$L38"}],"$L39","$L3a"]