What you'll learn
- How the central processing unit (CPU) executes instructions using the Arithmetic and Logic Unit (ALU), Control Unit (CU), registers and buses.
- What happens to the Program Counter (PC), MAR, MDR, CIR and Accumulator (ACC) during the Fetch-Decode-Execute cycle.
- How clock speed, number of cores, cache and pipelining affect processor performance.
- The difference between Von Neumann, Harvard and contemporary processor architectures.
The CPU: the instruction executor
A processor, usually called the CPU, is the part of the computer that runs program instructions. An instruction is a binary command that tells the CPU to do something, such as load a value, add two values, store a result or branch to another instruction.
An assembly language program is a low-level program written using short mnemonics, such as LDA, ADD and STA, that correspond closely to machine-code instructions. Each instruction usually contains an opcode, which says what operation to perform, and sometimes an operand, which is the data or address the instruction uses.
The CPU runs one simple instruction at a time
Even complex software is eventually executed as many simple machine-code instructions, fetched from memory, decoded by the Control Unit and carried out using registers, buses and the ALU.
Main parts of the CPU
Arithmetic and Logic Unit (ALU)
The Arithmetic and Logic Unit (ALU) performs calculations and logical operations. Arithmetic includes addition and subtraction. Logic includes comparisons such as “is this value zero?” or “is this value greater than another value?”.
The ALU often works closely with the Accumulator (ACC), a register used to store intermediate results of calculations.
Control Unit (CU)
The Control Unit (CU) coordinates the CPU. It decodes instructions, sends control signals to other components and manages the timing of operations.
The Control Unit does not usually perform calculations itself. Instead, it tells the ALU, registers and memory what to do.
Registers
A register is a very small, very fast storage location inside the CPU. Registers are faster to access than main memory, but there are far fewer of them.
| Register | Full name | Main job |
|---|---|---|
| PC | Program Counter | Stores the address of the next instruction to fetch |
| ACC | Accumulator | Stores intermediate calculation results |
| MAR | Memory Address Register | Stores the memory address currently being accessed |
| MDR | Memory Data Register | Stores data or instructions being transferred to or from memory |
| CIR | Current Instruction Register | Stores the instruction currently being decoded and executed |
MAR and MDR are not the same
The MAR holds an address. The MDR holds the actual data or instruction being transferred. If the CPU is fetching from memory address 120, 120 goes in the MAR; the contents found at address 120 go in the MDR.
Buses
A bus is a set of parallel wires or connections used to transfer data, addresses or control signals between components.
The address bus carries memory addresses, usually from the CPU to memory. The data bus carries data and instructions between CPU and memory, usually in both directions. The control bus carries signals such as read, write, clock and interrupt signals.
Assembly language instructions rely directly on these pathways. For example, an instruction such as LDA 20 means “load the value stored at memory address 20 into the accumulator”. To do that, the CPU must place address 20 in the MAR, signal a memory read on the control bus, receive the value through the data bus into the MDR, then copy it into the ACC.
The Fetch-Decode-Execute cycle
The Fetch-Decode-Execute cycle is the repeating process used by the CPU to run instructions.
Fetch
During fetch, the CPU gets the next instruction from main memory.
Typical register effects are:
- The address in the PC is copied to the MAR.
- A memory read is requested using the control bus.
- The instruction stored at that address is copied into the MDR.
- The instruction is copied from the MDR into the CIR.
- The PC is incremented so it points to the next instruction.
Decode
During decode, the Control Unit interprets the instruction in the CIR. It works out the opcode, whether an operand is needed and which components must be used.
Execute
During execute, the instruction is carried out. This might involve the ALU doing a calculation, the ACC being updated, data being stored back in memory, or the PC being changed by a branch instruction.
What the PC really stores
By the time an instruction is being decoded or executed, the PC usually already points to the next instruction. A branch instruction can overwrite the PC with a different address.
Tracing LDA and ADD through registers
Consider this simple LMC-style assembly program:
| Address | Instruction | Meaning |
|---|---|---|
| 00 | LDA 20 | Load the value at address 20 into ACC |
| 01 | ADD 21 | Add the value at address 21 to ACC |
| 02 | OUT | Output ACC |
| 03 | HLT | Stop |
| 20 | DAT 7 | Store data value 7 |
| 21 | DAT 5 | Store data value 5 |
- Starting with PC = 00, the CPU fetches the instruction at address 00. The PC value 00 is copied to the MAR, memory returns
LDA 20into the MDR, and the CIR becomesLDA 20. - The Control Unit decodes
LDA 20. The operand address 20 is placed in the MAR, memory returns the value 7 into the MDR, and the ACC becomes 7. - The next instruction,
ADD 21, is fetched from address 01 into the CIR, and the PC moves on to address 02. - The CPU executes
ADD 21by fetching the value 5 from address 21 into the MDR. The ALU adds ACC and MDR, so the ACC becomes 12.
Factors affecting CPU performance
Clock speed
Clock speed is the number of clock cycles per second, measured in hertz. A clock cycle is one timing pulse used to coordinate processor operations. A higher clock speed can mean more instructions processed per second, but only if other factors do not become limiting.
Estimating clock-speed effect
A task needs 6 billion clock cycles. CPU A runs at 3 GHz and CPU B runs at 2 GHz.
- Convert the clock speeds into cycles per second: 3 GHz is 3×1093 \times 10^93×109 cycles per second, and 2 GHz is 2×1092 \times 10^92×109 cycles per second.
- Use time=cyclescycles per second\text{time}=\frac{\text{cycles}}{\text{cycles per second}}time=cycles per secondcycles. CPU A takes 6×1093×109=2\frac{6 \times 10^9}{3 \times 10^9}=23×1096×109=2 seconds.
- CPU B takes 6×1092×109=3\frac{6 \times 10^9}{2 \times 10^9}=32×1096×109=3 seconds, so CPU A is faster here — assuming the same architecture, cache behaviour and cycles per instruction.
Number of cores
A core is a processing unit within a CPU that can fetch, decode and execute instructions. A multi-core CPU can run multiple instruction streams at the same time.
More cores help most when software is designed for parallel processing, where a task is split into parts that can run simultaneously. They do not automatically make a single sequential program faster.
Cache
Cache is a small amount of very fast memory close to, or inside, the CPU. It stores frequently used instructions and data so the CPU does not always have to wait for slower main memory.
A cache hit happens when the required data is found in cache. A cache miss happens when it is not, so the CPU must fetch it from main memory.
Clock speed is not everything
A processor with a higher clock speed can still perform worse if it has fewer cores, a smaller or slower cache, a less efficient architecture, or if the program cannot make use of its strengths.
Pipelining
Pipelining improves efficiency by overlapping the stages of several instructions. Instead of fully finishing one instruction before starting the next, the CPU might fetch one instruction while decoding another and executing a third.
This improves throughput, which means the number of instructions completed per unit time. It does not usually reduce the latency, which is the time taken for one individual instruction to pass through the whole pipeline.
| Clock cycle | Instruction 1 | Instruction 2 | Instruction 3 | Instruction 4 |
|---|---|---|---|---|
| 1 | Fetch | |||
| 2 | Decode | Fetch | ||
| 3 | Execute | Decode | Fetch | |
| 4 | Execute | Decode | Fetch | |
| 5 | Execute | Decode | ||
| 6 | Execute |
Estimating pipeline throughput
Suppose each instruction has 3 stages: fetch, decode and execute. Each stage takes 1 clock cycle. There are 4 instructions.
- Without pipelining, each instruction takes 3 cycles, so 4 instructions take 4×3=124 \times 3=124×3=12 cycles.
- With pipelining and no delays, the first instruction still takes 3 cycles to complete.
- After that, one more instruction completes each cycle, so the total is 3+(4−1)=63+(4-1)=63+(4−1)=6 cycles.
A pipeline hazard is a situation that prevents the next instruction from safely moving through the pipeline. For example, a branch may change the PC, or one instruction may need the result of a previous instruction that has not finished yet. The CPU may need to stall or flush part of the pipeline.
Processor architectures
An architecture is the overall design and organisation of a computer system, including how the CPU, memory and buses are arranged.
Von Neumann architecture
In Von Neumann architecture, instructions and data are stored in the same main memory and travel along the same shared bus system.
This is simple and flexible, because programs can be stored and treated like data. However, it can cause the Von Neumann bottleneck, where instruction fetches and data transfers compete for the same route.
Harvard architecture
In Harvard architecture, instructions and data are stored in separate memories and use separate buses.
This allows an instruction and data item to be fetched at the same time, improving throughput. It is common in embedded systems and digital signal processors where predictable performance matters.
Contemporary processor architecture
Most modern general-purpose processors are not purely Von Neumann or purely Harvard. They often use a modified Harvard architecture: main memory may store both instructions and data, but the CPU has separate instruction and data caches internally.
Contemporary processors also commonly use multiple cores, pipelining, branch prediction and layers of cache to reduce waiting and increase throughput.
Modern CPUs combine ideas
At main memory level, many systems look Von Neumann. Inside the processor, separate instruction and data caches make them behave partly like Harvard systems for speed.
In the exam
- For register questions, name the register and its role precisely: PC = next instruction address, MAR = memory address, MDR = data or instruction transfer, CIR = current instruction, ACC = intermediate result.
- For Fetch-Decode-Execute questions, describe the register changes, not just “fetch, decode, execute”.
- For performance questions, avoid saying one factor “always” makes a CPU faster. Explain the condition: parallel software for more cores, cache hits for cache, and same architecture when comparing clock speed.
Check yourself
- What is the difference between the MAR and the MDR during an instruction fetch?
- Why might adding more cores fail to speed up a particular program?
- How does a modified Harvard architecture combine features of Von Neumann and Harvard designs?
