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With $n$ independent inputs, the total number of input combinations, and therefore truth-table rows, is $2^n$."},{"text":"$$2n$","correct":false,"explanation":"Multiplying the number of inputs by two ignores the way independent binary choices combine. There are two choices for each of $n$ inputs, giving $2^n$ rows."},{"text":"$$n^2$","correct":false,"explanation":"Squaring the number of inputs is not the rule for counting binary combinations. Each additional input doubles the combinations, so a truth table requires $2^n$ rows."},{"text":"$$2^{n-1}$","correct":false,"explanation":"This omits one input when applying the exponent, halving the required number of rows. All $n$ binary inputs must be included, producing $2^n$ combinations."}]},{"id":"132f353e-69f7-44ed-94b7-5561a99a47e8","cardType":"basic","points":1,"front":"In a logic gate symbol, what does a small circle (inversion bubble) represent?","back":"A NOT operation (it inverts the signal).","mcqOptions":[{"text":"A NOT operation (it inverts the signal).","correct":true,"explanation":"An inversion bubble negates the signal at the terminal where it appears. It changes a binary 1 to 0 and a binary 0 to 1."},{"text":"An AND operation (it combines both signals).","correct":false,"explanation":"An AND operation is represented by the gate’s main shape, not by a small circle. The circle denotes a NOT operation that inverts the signal."},{"text":"An OR operation (it accepts either signal).","correct":false,"explanation":"An OR operation is indicated by the gate’s curved symbol rather than an inversion bubble. A small circle represents NOT and reverses the signal’s binary value."},{"text":"A DELAY operation (it stores the signal).","correct":false,"explanation":"A small circle does not store or delay a signal; storage requires a sequential component such as a flip-flop. The bubble represents a NOT operation."}]},{"id":"80458031-86ea-4faf-87b5-5315d0440ea0","cardType":"cloze","points":null,"front":"In Boolean notation, $\\text{[...]}$ represents an AND gate, while $Q = A + B$ represents an OR gate.","back":"In Boolean notation, $\\boxed{Q = A \\cdot B}$ represents an AND gate, while $Q = A + B$ represents an OR gate.","mcqOptions":[{"text":"$$Q = A \\cdot B$","correct":true,"explanation":"In Boolean algebra, multiplication or a centred dot denotes logical AND. The output $Q$ is 1 only when both $A$ and $B$ are 1."},{"text":"$$Q = A + B$","correct":false,"explanation":"The plus sign denotes logical OR, not AND. An AND gate is represented by $Q = A \\cdot B$ and outputs 1 only when both inputs are 1."},{"text":"$$Q = \\overline{A \\cdot B}$","correct":false,"explanation":"The overline negates the result, so this expression represents NAND rather than AND. Without the inversion, the correct AND expression is $Q = A \\cdot B$."},{"text":"$$Q = A \\oplus B$","correct":false,"explanation":"The exclusive-OR symbol represents XOR, which is 1 when the inputs differ. AND instead uses multiplication notation: $Q = A \\cdot B$."}]},{"id":"fcffc6a7-0327-4e5a-b644-a3cc2521ac98","cardType":"cloze","points":null,"front":"In Boolean notation, $Q = A \\cdot B$ represents an AND gate, while $\\text{[...]}$ represents an OR gate.","back":"In Boolean notation, $Q = A \\cdot B$ represents an AND gate, while $\\boxed{Q = A + B}$ represents an OR gate.","mcqOptions":[{"text":"$$Q = A + B$","correct":true,"explanation":"In Boolean algebra, the plus sign denotes logical OR. The output $Q$ is 1 when $A$, $B$, or both inputs are 1."},{"text":"$$Q = A \\cdot B$","correct":false,"explanation":"A centred dot denotes logical AND, not OR. The Boolean expression for OR is $Q = A + B$, which is true when at least one input is true."},{"text":"$$Q = \\overline{A + B}$","correct":false,"explanation":"The overline negates the OR result, making this a NOR expression. An OR gate has no inversion and is written $Q = A + B$."},{"text":"$$Q = A \\oplus B$","correct":false,"explanation":"The exclusive-OR symbol excludes the case where both inputs are 1. Ordinary OR includes that case and is represented by $Q = A + B$."}]},{"id":"9d984eb4-942f-4b40-8db4-1fe77e928910","cardType":"basic","points":2,"front":"How does the output of a 2-input XOR gate differ from an OR gate when both inputs are 1?","back":"

XOR output is 0 (exactly one input must be 1).
OR output is 1 (at least one input must be 1).

","mcqOptions":[{"text":"

XOR output is 0 (exactly one input must be 1).
OR output is 1 (at least one input must be 1).

","correct":true,"explanation":"XOR is true only when exactly one input is 1, so inputs 1 and 1 produce 0. OR requires at least one 1, so it produces 1."},{"text":"

XOR output is 1 (at least one input must be 1).
OR output is 0 (exactly one input must be 1).

","correct":false,"explanation":"This reverses the two outputs. With inputs 1 and 1, XOR produces 0 because the inputs match, while OR produces 1 because at least one input is 1."},{"text":"

XOR output is 1 (at least one input must be 1).
OR output is 1 (at least one input must be 1).

","correct":false,"explanation":"This treats XOR like an ordinary OR gate. XOR rejects the case where both inputs are 1, so XOR outputs 0 while OR outputs 1."},{"text":"

XOR output is 0 (exactly one input must be 1).
OR output is 0 (exactly one input must be 1).

","correct":false,"explanation":"This treats OR as though two true inputs cancel each other. OR remains true when both inputs are 1, while XOR outputs 0 because exactly one input must be 1."}]},{"id":"56fbd013-d9d0-412f-abe9-29e19011e921","cardType":"basic","points":1,"front":"What is the Boolean expression for a NAND gate?","back":"$$Q = \\overline{A \\cdot B}$","mcqOptions":[{"text":"$$Q = \\overline{A \\cdot B}$","correct":true,"explanation":"A NAND gate performs AND and then negates the result. The product $A \\cdot B$ is therefore placed under an overline to show inversion."},{"text":"$$Q = A \\cdot B$","correct":false,"explanation":"This is the expression for an AND gate because it lacks the required inversion. NAND negates the AND result, giving $Q = \\overline{A \\cdot B}$."},{"text":"$$Q = \\overline{A + B}$","correct":false,"explanation":"Negating a sum produces NOR, not NAND. NAND negates the product of the inputs, so its expression is $Q = \\overline{A \\cdot B}$."},{"text":"$$Q = A + B$","correct":false,"explanation":"The plus sign represents OR, and there is no inversion here. NAND requires an AND operation followed by NOT, written $Q = \\overline{A \\cdot B}$."}]},{"id":"01c3b426-c9fb-4840-8507-d79b45e3c03b","cardType":"basic","points":1,"front":"What is the Boolean expression for a NOR gate?","back":"$$Q = \\overline{A + B}$","mcqOptions":[{"text":"$$Q = \\overline{A + B}$","correct":true,"explanation":"A NOR gate performs OR and then negates the result. The sum $A + B$ is placed under an overline to show that the OR output is inverted."},{"text":"$$Q = A + B$","correct":false,"explanation":"This is an OR expression because it lacks the required inversion. NOR negates the result of OR, giving the expression $Q = \\overline{A + B}$."},{"text":"$$Q = \\overline{A \\cdot B}$","correct":false,"explanation":"Negating a product gives NAND rather than NOR. NOR negates the sum of the inputs, so the correct expression is $Q = \\overline{A + B}$."},{"text":"$$Q = A \\cdot B$","correct":false,"explanation":"The centred dot represents AND, and there is no inversion in this expression. NOR performs an inverted OR operation, written $Q = \\overline{A + B}$."}]},{"id":"aed093eb-6462-4e3f-9877-2a9c98f7f7b8","cardType":"cloze","points":null,"front":"A [ ] circuit's output depends only on current inputs, whereas a D-type flip-flop can store a bit.","back":"A combinational circuit's output depends only on current inputs, whereas a D-type flip-flop can store a bit.","mcqOptions":[{"text":"combinational","correct":true,"explanation":"A combinational circuit has no stored state, so its output is determined entirely by its present inputs. A D-type flip-flop is sequential because it stores a bit."},{"text":"sequential","correct":false,"explanation":"A sequential circuit’s output can depend on stored state as well as current inputs. The term for a circuit determined only by present inputs is combinational."},{"text":"stateful","correct":false,"explanation":"Stateful means that previous inputs or stored data can affect the output, contradicting the sentence. A circuit whose output depends only on current inputs is combinational."},{"text":"clocked","correct":false,"explanation":"A clocked circuit commonly updates or stores state in response to a clock signal, so its output is not necessarily based only on present inputs. The required term is combinational."}]},{"id":"86175391-9419-4e5a-897a-e5a2a156e146","cardType":"cloze","points":null,"front":"A combinational circuit's output depends only on current inputs, whereas a [ ] can store a bit.","back":"A combinational circuit's output depends only on current inputs, whereas a D-type flip-flop can store a bit.","mcqOptions":[{"text":"D-type flip-flop","correct":true,"explanation":"A D-type flip-flop retains one binary value and updates it in response to a clock edge, so it provides the storage absent from combinational circuits."},{"text":"two-input AND gate","correct":false,"explanation":"An AND gate produces a combinational output from its current inputs and has no memory. A D-type flip-flop is the component that can store one bit."},{"text":"2-to-1 multiplexer","correct":false,"explanation":"A multiplexer selects between current input values but does not retain them after they change. A D-type flip-flop can store a bit."},{"text":"half-adder circuit","correct":false,"explanation":"A half-adder calculates sum and carry outputs from two current inputs, so it has no storage. A D-type flip-flop can retain one bit."}]},{"id":"4a5d47a6-d4c9-451f-950d-c007ef4faaf2","cardType":"basic","points":1,"front":"When drawing a circuit from the expression $Q = (A \\cdot B) + C$, what determines which gate is drawn first?","back":"Brackets (sub-expressions must be built before they are fed into subsequent gates).","mcqOptions":[{"text":"Brackets (sub-expressions must be built before they are fed into subsequent gates).","correct":true,"explanation":"Brackets identify the sub-expression that must be implemented first. Here, the AND output for $A \\cdot B$ is produced before being fed into the OR gate."},{"text":"Left-to-right order (gates are drawn in the order their symbols appear).","correct":false,"explanation":"Boolean expressions are not implemented simply by reading symbols from left to right. Brackets determine that $A \\cdot B$ must be constructed before the final OR operation."},{"text":"The output gate (the final operation must always be drawn first).","correct":false,"explanation":"The output gate represents the final operation, so it is normally connected after the gates for its sub-expressions. Brackets determine which sub-expression is built first."},{"text":"Input labels (alphabetically earlier inputs are connected first).","correct":false,"explanation":"Input names identify signals but do not determine construction order. The bracketed sub-expression is implemented first and its result is fed into the subsequent gate."}]},{"id":"e422e6ca-0b71-4000-88f2-ab6e14acbad7","cardType":"basic","points":2,"front":"What two gates are used to construct a half-adder?","back":"

XOR (for the Sum bit)
AND (for the Carry bit)

","mcqOptions":[{"text":"

XOR (for the Sum bit)
AND (for the Carry bit)

","correct":true,"explanation":"XOR outputs the Sum bit because it is 1 when exactly one input is 1, while AND outputs the Carry bit when both inputs are 1."},{"text":"

OR (for the Sum bit)
AND (for the Carry bit)

","correct":false,"explanation":"OR would output 1 when both inputs are 1, but a half-adder’s Sum must then be 0. XOR generates Sum, while AND generates Carry."},{"text":"

XOR (for the Sum bit)
OR (for the Carry bit)

","correct":false,"explanation":"OR cannot generate the Carry bit because it outputs 1 when only one input is 1. Carry requires both inputs to be 1, so it uses AND."},{"text":"

AND (for the Sum bit)
XOR (for the Carry bit)

","correct":false,"explanation":"AND does not produce the required Sum pattern, and XOR does not identify when both inputs are 1. A half-adder uses XOR for Sum and AND for Carry."}]},{"id":"708dadf0-bb1a-4e4d-9e03-79f717cc21d9","cardType":"basic","points":1,"front":"What are the three inputs of a full-adder circuit?","back":"

Input A
Input B
Carry-in ($C_{\\text{in}}$)

","mcqOptions":[{"text":"

Input A
Input B
Carry-in ($C_{\\text{in}}$)

","correct":true,"explanation":"A full-adder adds two operand bits, $A$ and $B$, together with the carry produced by the preceding, less significant binary column."},{"text":"

Input A
Input B
Carry-out ($C_{\\text{out}}$)

","correct":false,"explanation":"Carry-out is produced by the full-adder rather than supplied to it. The third input is Carry-in, received from the preceding binary column."},{"text":"

Input A
Output Sum
Carry-in ($C_{\\text{in}}$)

","correct":false,"explanation":"Sum is an output, not one of the values entering the full-adder. Its three inputs are $A$, $B$, and Carry-in."},{"text":"

Input B
Output Sum
Carry-out ($C_{\\text{out}}$)

","correct":false,"explanation":"Both Sum and Carry-out are results produced by the circuit, leaving this list with only one genuine input. The inputs are $A$, $B$, and Carry-in."}]},{"id":"46b1f6c6-fdb6-415c-bcef-3c56224def7c","cardType":"basic","points":2,"front":"Which components are required to build a full-adder from simpler units?","back":"

Two half-adders
One OR gate (to combine carry bits)

","mcqOptions":[{"text":"

Two half-adders
One OR gate (to combine carry bits)

","correct":true,"explanation":"The first half-adder combines the operand bits and the second includes Carry-in. Their two possible carry results are combined using an OR gate."},{"text":"

Two half-adders
One AND gate (to combine carry bits)

","correct":false,"explanation":"The two half-adders are appropriate, but their carry outputs represent alternative ways to produce a carry and must be combined with OR, not AND."},{"text":"

One half-adder
One OR gate (to combine carry bits)

","correct":false,"explanation":"One half-adder can process only two input bits, so it cannot fully incorporate $A$, $B$, and Carry-in. Two half-adders and one OR gate are required."},{"text":"

Two XOR gates
One AND gate (to produce the carry bit)

","correct":false,"explanation":"XOR and AND gates form one half-adder, not the complete three-input circuit. A full-adder construction requires two half-adders and an OR gate."}]},{"id":"040218de-8421-4ba3-9ab0-e2660f34af2b","cardType":"cloze","points":null,"front":"The Boolean expression for the Sum ($S$) in a full-adder is $\\text{[...]}$.","back":"The Boolean expression for the Sum ($S$) in a full-adder is $\\boxed{S = A \\oplus B \\oplus C_{\\text{in}}}$.","mcqOptions":[{"text":"$$S = A \\oplus B \\oplus C_{\\text{in}}$","correct":true,"explanation":"The Sum bit is 1 when an odd number of the three inputs are 1. Chaining XOR operations gives exactly this parity behaviour."},{"text":"$$S = A + B + C_{\\text{in}}$","correct":false,"explanation":"Using OR would make the Sum 1 whenever any input is 1, including cases with two inputs set. Sum requires odd parity, so XOR is used."},{"text":"$$S = A \\cdot B \\cdot C_{\\text{in}}$","correct":false,"explanation":"Using AND would produce 1 only when all three inputs are 1 and misses other odd-parity cases. The Sum is the XOR of all three inputs."},{"text":"$$S = A \\oplus B$","correct":false,"explanation":"This expression includes only $A$ and $B$, so it ignores the incoming carry. A full-adder’s Sum must XOR all three input bits."}]},{"id":"9e02e77b-2a44-4669-9820-c44bdeae0e74","cardType":"basic","points":2,"front":"In a full-adder, what is the Sum ($S$) and Carry-out ($C_{\\text{out}}$) if $A=1, B=1, C_{\\text{in}}=1$?","back":"

$S = 1$
$C_{\\text{out}} = 1$

","mcqOptions":[{"text":"

$S = 1$
$C_{\\text{out}} = 1$

","correct":true,"explanation":"Adding the three input bits gives decimal 3, which is binary $11$. The low-order bit is the Sum and the high-order bit is Carry-out, so both are 1."},{"text":"

$S = 0$
$C_{\\text{out}} = 1$

","correct":false,"explanation":"The three input bits total decimal 3, or binary $11$, not $10$. Therefore the Sum bit is 1 as well as the Carry-out bit."},{"text":"

$S = 1$
$C_{\\text{out}} = 0$

","correct":false,"explanation":"Although the Sum bit is 1, adding three 1s exceeds a single binary digit and generates a carry. The Carry-out must therefore also be 1."},{"text":"

$S = 0$
$C_{\\text{out}} = 0$

","correct":false,"explanation":"This treats the three inputs as if they produced no result. Their total is decimal 3, represented as binary $11$, so both outputs are 1."}]},{"id":"685fa86c-9902-46a4-b8f7-b097af7fd346","cardType":"cloze","points":null,"front":"A [ ] is a timing signal that changes between 0 and 1, and an edge is the instant that state change occurs.","back":"A clock is a timing signal that changes between 0 and 1, and an edge is the instant that state change occurs.","mcqOptions":[{"text":"clock","correct":true,"explanation":"A clock repeatedly alternates between low and high logic levels to coordinate sequential circuits. Each transition is called a rising or falling edge."},{"text":"data bus","correct":false,"explanation":"A data bus carries multiple binary values between components rather than providing a regular timing signal. The alternating timing signal is called a clock."},{"text":"logic gate","correct":false,"explanation":"A logic gate performs a Boolean operation on its inputs and does not inherently generate the circuit’s timing transitions. That timing signal is a clock."},{"text":"multiplexer","correct":false,"explanation":"A multiplexer selects one of several data inputs using selection lines; it is not the regular timing signal. A clock alternates between 0 and 1."}]},{"id":"71683b6b-9df2-4df6-9714-d35724d747c7","cardType":"cloze","points":null,"front":"A clock is a timing signal that changes between 0 and 1, and an [ ] is the instant that state change occurs.","back":"A clock is a timing signal that changes between 0 and 1, and an edge is the instant that state change occurs.","mcqOptions":[{"text":"edge","correct":true,"explanation":"An edge is the precise instant when a clock signal changes state. A rising edge changes from 0 to 1, while a falling edge changes from 1 to 0."},{"text":"interval","correct":false,"explanation":"An interval is a period of time rather than an instant of change. The correct term is edge, which identifies the moment when the clock changes state."},{"text":"oscillation","correct":false,"explanation":"An oscillation is a repeated variation between states, not the instant of one state change. That particular instant is called an edge."},{"text":"impulse","correct":false,"explanation":"An impulse is a brief signal or input, not the standard term for a clock transition. The instant when the clock changes between 0 and 1 is an edge."}]},{"id":"d5b0a6e8-eb02-4642-8072-c683c42c2822","cardType":"basic","points":2,"front":"How does an edge-triggered D-type flip-flop behave when the active clock edge occurs?","back":"The output $Q$ copies the value of the data input $D$.","mcqOptions":[{"text":"The output $Q$ copies the value of the data input $D$.","correct":true,"explanation":"At the active clock edge, the flip-flop samples the data input $D$ and transfers that value to $Q$, where it remains until another active edge."},{"text":"The output $Q$ toggles to the opposite of its current value.","correct":false,"explanation":"Toggling is characteristic of a T-type flip-flop, not a D-type flip-flop. At the active edge, $Q$ copies the current value of $D$."},{"text":"The output $Q$ copies every change in the data input $D$.","correct":false,"explanation":"This describes continuous or transparent behaviour rather than edge-triggered operation. A D-type flip-flop copies $D$ only when the active clock edge occurs."},{"text":"The output $Q$ resets to 0 regardless of the data input $D$.","correct":false,"explanation":"The active clock edge does not automatically reset the flip-flop. It causes $Q$ to copy $D$, so $Q$ may become either 0 or 1."}]},{"id":"50845687-34a4-4670-9d0e-dd50f0d9af70","cardType":"basic","points":1,"front":"What happens to the output $Q$ of a D-type flip-flop between active clock edges?","back":"It holds its previous value (acting as a memory unit).","mcqOptions":[{"text":"It holds its previous value (acting as a memory unit).","correct":true,"explanation":"Between active clock edges, the flip-flop does not sample $D$, so $Q$ retains its previous state. This ability to preserve one bit gives it memory."},{"text":"It copies every change at the data input $D$.","correct":false,"explanation":"Copying every change would make the device transparent rather than edge-triggered. Between active edges, $Q$ holds its previous value regardless of changes at $D$."},{"text":"It toggles to the opposite value after each clock cycle.","correct":false,"explanation":"Automatic toggling is associated with T-type behaviour. A D-type flip-flop holds its previous value between active edges and changes only by sampling $D$ at an edge."},{"text":"It returns to 0 until the next active clock edge.","correct":false,"explanation":"A D-type flip-flop does not automatically return to 0 between edges. It holds whichever value was stored at the most recent active clock edge."}]},{"id":"b44cbf62-5e50-424d-8273-f12634cc0ed5","cardType":"basic","points":1,"front":"What is the Boolean expression for the Carry bit in a half-adder?","back":"$$C = A \\cdot B$","mcqOptions":[{"text":"$$C = A \\cdot B$","correct":true,"explanation":"A half-adder produces a carry only when both inputs are 1. This is the AND condition, represented in Boolean algebra by $A \\cdot B$."},{"text":"$$C = A + B$","correct":false,"explanation":"The $+$ operator represents OR, which gives 1 when either input is 1. Carry requires both inputs to be 1, so $C = A \\cdot B$."},{"text":"$$C = A \\oplus B$","correct":false,"explanation":"XOR gives the half-adder Sum bit because it is 1 when exactly one input is 1. The Carry bit uses AND, so $C = A \\cdot B$."},{"text":"$$C = \\overline{A \\cdot B}$","correct":false,"explanation":"This expression is NAND, so it produces 0 when both inputs are 1. A carry must be 1 in that case, requiring $C = A \\cdot B$."}]},{"id":"5f08b446-a75b-459a-87e0-3c99ac9917a8","cardType":"basic","points":1,"front":"If $Q = \\overline{Q}$ is shown on a D-type flip-flop symbol, what does it represent?","back":"The inverse of output $Q$.","mcqOptions":[{"text":"The inverse of output $Q$.","correct":true,"explanation":"A bar over a Boolean variable denotes logical NOT. Therefore, $\\overline{Q}$ always has the opposite value to $Q$: it is 1 when $Q$ is 0, and vice versa."},{"text":"The stored value of output $Q$.","correct":false,"explanation":"The uncomplemented $Q$ output represents the stored value itself. A bar indicates logical inversion, so $\\overline{Q}$ is the inverse of output $Q$."},{"text":"The input value copied from $D$.","correct":false,"explanation":"At an active edge, $Q$ may copy $D$, but the barred symbol specifically denotes complementation. It represents the inverse of $Q$, not the data input itself."},{"text":"The clock state controlling output $Q$.","correct":false,"explanation":"The clock determines when the stored value can change, but it is represented by a separate input. The barred $Q$ symbol denotes the inverse of output $Q$."}]},{"id":"d3e08349-3c4f-43b3-aa91-f7b3011a167b","cardType":"cloze","points":null,"front":"In Boolean logic, $1 + 1$ equals [ ], because the $+$ symbol represents the OR operation.","back":"In Boolean logic, $1 + 1$ equals 1, because the $+$ symbol represents the OR operation.","mcqOptions":[{"text":"1","correct":true,"explanation":"Boolean addition represents OR rather than ordinary arithmetic. Since OR produces 1 when either or both operands are 1, $1 + 1$ evaluates to 1."},{"text":"0","correct":false,"explanation":"A result of 0 confuses OR with XOR, where two identical 1 inputs produce 0. Boolean $+$ means OR, so $1 + 1$ equals 1."},{"text":"2","correct":false,"explanation":"This applies ordinary arithmetic addition instead of Boolean OR. Boolean values remain either 0 or 1, and OR with two 1 inputs produces 1."},{"text":"10","correct":false,"explanation":"This treats the expression as binary arithmetic, where $1 + 1$ gives $10_2$. The $+$ symbol here represents Boolean OR, so the result is 1."}]},{"id":"db3b7aea-2b1f-47cd-a1d0-a9d3819aa262","cardType":"cloze","points":null,"front":"In Boolean logic, $1 + 1$ equals 1, because the $+$ symbol represents the [ ] operation.","back":"In Boolean logic, $1 + 1$ equals 1, because the $+$ symbol represents the OR operation.","mcqOptions":[{"text":"OR","correct":true,"explanation":"In Boolean algebra, the $+$ symbol denotes OR. OR produces 1 when at least one input is 1, so applying it to 1 and 1 gives 1."},{"text":"AND","correct":false,"explanation":"AND is normally represented by a dot or adjacency, not by $+$. The $+$ symbol represents OR, which also explains why $1 + 1$ equals 1."},{"text":"XOR","correct":false,"explanation":"XOR produces 1 only when the inputs differ, so $1 \\mathbin{\\mathrm{XOR}} 1$ would equal 0. The $+$ symbol in Boolean algebra represents OR."},{"text":"NOR","correct":false,"explanation":"NOR is the inverse of OR and would produce 0 for two 1 inputs. The uncomplemented $+$ operator represents OR, giving a result of 1."}]},{"id":"417043a1-012d-4e7e-a397-00b2705aaf31","cardType":"basic","points":1,"front":"Why are intermediate columns used when completing a truth table for a complex circuit?","back":"To track the output of each gate individually before reaching the final result.","mcqOptions":[{"text":"To track the output of each gate individually before reaching the final result.","correct":true,"explanation":"Intermediate columns break the circuit into stages by recording each gate output. Those values can then be used systematically as inputs when evaluating later gates."},{"text":"To reduce the number of input combinations that must be evaluated.","correct":false,"explanation":"The number of input combinations is fixed at $2^n$ for $n$ inputs and is not reduced by extra columns. Intermediate columns record each gate output."},{"text":"To show the output of only the final gate without evaluating earlier gates.","correct":false,"explanation":"A final gate cannot be evaluated reliably until the outputs feeding it are known. Intermediate columns calculate and track the output of each earlier gate individually."},{"text":"To replace the need to apply Boolean operators when finding the final result.","correct":false,"explanation":"Boolean operations must still be applied to every gate. Intermediate columns organise these calculations by recording each gate output before it is used in a later stage."}]}]}],"examCountdown":{"examDate":"2027-05-11","paperLabel":"Paper 1"},"heading":"Logic gates","title":"Logic gates Flashcards","topbar":{"backHref":"/as-level/computer-science/aqa/flashcards"},"topicSidebar":"$L37"}]}],"topicId":"2f095835-a97f-5497-85f1-d6ebc0a34788","walled":"$L38"}],"$L39","$L3a"]