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Processor
Main memory
I/O controllers
Buses

","mcqOptions":[{"text":"

Processor
Main memory
I/O controllers
Buses

","correct":true,"explanation":"These four components cover processing, temporary storage, communication with peripherals, and the shared pathways carrying signals between components."},{"text":"

Processor
Main memory
Secondary storage
Power supply

","correct":false,"explanation":"Secondary storage and the power supply are important hardware, but they are not two of the four primary internal components in this model. The correct set includes I/O controllers and buses instead."},{"text":"

Processor
Cache memory
Registers
Graphics card

","correct":false,"explanation":"Cache and registers are parts of, or closely associated with, the processor, while a graphics card is a specialised device. The four primary components are processor, main memory, I/O controllers, and buses."},{"text":"

Motherboard
Hard disk
Cooling system
Network interface

","correct":false,"explanation":"These are individual hardware devices or support components rather than the four broad categories used to describe internal organisation. That model identifies the processor, main memory, I/O controllers, and buses."}]},{"id":"e66b55af-75f5-423e-86a9-8f3e5cd49f00","cardType":"basic","points":1,"front":"What is the primary role of the processor (CPU)?","back":"To execute program instructions by fetching, decoding, and carrying out arithmetic, logic, and control operations.","mcqOptions":[{"text":"To execute program instructions by fetching, decoding, and carrying out arithmetic, logic, and control operations.","correct":true,"explanation":"The processor repeatedly fetches instructions, decodes their meaning, and performs the required arithmetic, logical, or control operation, allowing stored programs to run."},{"text":"To store program instructions permanently by saving them on magnetic or solid-state media.","correct":false,"explanation":"Permanent storage is the role of secondary storage, not the processor. The processor runs instructions by fetching, decoding, and carrying out arithmetic, logic, and control operations."},{"text":"To connect peripherals directly by converting their signals into network packets.","correct":false,"explanation":"I/O controllers handle communication differences between peripherals and the processor, while networking equipment handles packet communication. The processor's primary role is executing instructions and operations."},{"text":"To provide electrical power by regulating voltage for every internal component.","correct":false,"explanation":"The power supply distributes regulated electrical power; it does not perform program execution. The processor instead fetches, decodes, and carries out instructions and their operations."}]},{"id":"b22d6c9c-a44e-4b90-a371-044753e79ed4","cardType":"cloze","points":null,"front":"Main memory is [ ], meaning its contents are lost when power is removed.","back":"Main memory is volatile, meaning its contents are lost when power is removed.","mcqOptions":[{"text":"volatile","correct":true,"explanation":"Volatile memory requires power to retain its contents, so data stored in main memory disappears when the computer's power is removed."},{"text":"non-volatile","correct":false,"explanation":"Non-volatile memory retains its contents without power, which is the opposite of the property described. Main memory is generally volatile, so its contents are lost when power is removed."},{"text":"persistent","correct":false,"explanation":"Persistent storage keeps data after power is removed, making this the opposite of the required property. The correct term for memory that loses its contents is volatile."},{"text":"permanent","correct":false,"explanation":"Permanent storage is intended to preserve information without continuous power. Main memory instead loses its contents when power is removed, so it is described as volatile."}]},{"id":"66e8c7fc-7dc3-4ba9-9559-d1b795b86ca4","cardType":"cloze","points":null,"front":"Main memory is volatile, meaning its contents are lost when [ ].","back":"Main memory is volatile, meaning its contents are lost when power is removed.","mcqOptions":[{"text":"power is removed","correct":true,"explanation":"Volatile memory depends on electrical power to maintain its contents. Once the power is removed, the stored data is lost."},{"text":"the processor is reset","correct":false,"explanation":"Resetting the processor does not normally remove power from main memory, so its contents are not necessarily lost. Volatile contents disappear when power is removed."},{"text":"the computer is restarted","correct":false,"explanation":"A restart may preserve power to memory during the reboot process, so it does not define the loss of volatile contents. The defining event is power removal."},{"text":"the system enters sleep mode","correct":false,"explanation":"Sleep mode usually continues supplying enough power to preserve main memory, allowing the system to resume. Volatile contents are lost when the power supply is removed."}]},{"id":"8e450e39-e1fe-4dce-8c5f-a067e743a788","cardType":"basic","points":1,"front":"Why must a program be loaded into main memory before it can be run?","back":"The processor cannot execute instructions directly from secondary storage; it can only fetch them from fast, directly accessible main memory.","mcqOptions":[{"text":"The processor cannot execute instructions directly from secondary storage; it can only fetch them from fast, directly accessible main memory.","correct":true,"explanation":"Secondary storage is too slow and is not directly accessed by the processor for normal instruction execution. Loading the program into main memory makes its instructions available for fetching."},{"text":"The processor can execute instructions directly from secondary storage; it can only fetch them from fast, directly accessible main memory.","correct":false,"explanation":"This reverses the key limitation: processors cannot normally execute instructions directly from secondary storage. Instructions must first be loaded into fast, directly accessible main memory."},{"text":"The processor cannot execute instructions directly from main memory; it can only fetch them from slow, indirectly accessible secondary storage.","correct":false,"explanation":"This swaps the roles of the two storage types. The processor fetches instructions from directly accessible main memory, while secondary storage holds programs before loading."},{"text":"The processor can execute instructions directly from either storage type; it selects whichever has the larger capacity.","correct":false,"explanation":"Capacity does not determine where instructions are executed, and secondary storage is not a direct execution source. Programs must be loaded into main memory before the processor runs them."}]},{"id":"04dbea5a-498e-4636-933b-8e98d09e8ade","cardType":"basic","points":2,"front":"What are the two main reasons I/O controllers are needed to interface with peripherals?","back":"

Peripherals use different timing, voltages, or data formats than the processor.
The controller provides a standard interface to simplify communication.

","mcqOptions":[{"text":"

Peripherals use different timing, voltages, or data formats than the processor.
The controller provides a standard interface to simplify communication.

","correct":true,"explanation":"Peripherals may communicate with different timing, voltage levels, or formats, so the controller adapts between them. It also presents a standard interface that makes communication simpler."},{"text":"

Peripherals use different instruction sets or storage capacities than the processor.
The controller provides a temporary storage area to simplify communication.

","correct":false,"explanation":"The important mismatches concern timing, voltages, and data formats, while the controller's key service is a standard interface. Instruction sets and temporary storage are not the two stated reasons."},{"text":"

Peripherals use different programming languages or file types than the processor.
The controller provides a separate processor core to simplify communication.

","correct":false,"explanation":"Peripheral interfacing is not primarily about programming languages or file types, and an I/O controller need not be a processor core. It adapts physical and data communication differences."},{"text":"

Peripherals use different screen resolutions or user accounts than the processor.
The controller provides a permanent backup to simplify communication.

","correct":false,"explanation":"Screen resolution and user accounts are not general interface mismatches, and controllers do not provide permanent backups. The relevant issues are timing, voltages, formats, and standardisation."}]},{"id":"3385bd7f-b912-4a4c-bb92-6e63ffb60f5a","cardType":"cloze","points":null,"front":"A [ ] is a shared set of physical connections used to transfer signals between computer components.","back":"A bus is a shared set of physical connections used to transfer signals between computer components.","mcqOptions":[{"text":"bus","correct":true,"explanation":"A bus is a shared collection of physical connections that allows signals to travel between computer components, such as the processor, memory, and I/O controllers."},{"text":"port","correct":false,"explanation":"A port is a connection point for attaching a device, not the shared set of connections carrying signals between multiple computer components. That shared pathway is called a bus."},{"text":"protocol","correct":false,"explanation":"A protocol is a set of communication rules, whereas the definition describes physical connections. The physical shared pathway used to transfer signals is a bus."},{"text":"register","correct":false,"explanation":"A register is a small, fast storage location inside the processor, not a shared physical communication pathway. The described connections between components form a bus."}]},{"id":"d2ea0121-1f7e-4fc3-a53c-761517e24904","cardType":"cloze","points":null,"front":"A bus is a shared set of physical connections used to transfer [ ] between computer components.","back":"A bus is a shared set of physical connections used to transfer signals between computer components.","mcqOptions":[{"text":"signals","correct":true,"explanation":"Buses carry electrical or electronic signals between components. These signals can represent data, addresses, and control information during communication within the computer."},{"text":"files","correct":false,"explanation":"Files are organised collections of stored data, not the electrical or electronic information carried across component connections. A bus transfers signals between components."},{"text":"programs","correct":false,"explanation":"Programs consist of instructions and data, but they are not the physical entities named in this definition. The bus carries signals representing information between components."},{"text":"users","correct":false,"explanation":"Users interact with a computer but are not transmitted between its internal components. The shared connections carry signals, which represent data, addresses, and control information."}]},{"id":"55f361bc-356f-4cb8-93ce-c3a4e76d4b16","cardType":"basic","points":1,"front":"Which bus is used to specify the memory location or I/O device the processor wants to access?","back":"The address bus.","mcqOptions":[{"text":"The address bus.","correct":true,"explanation":"The address bus carries the binary address of the memory location or I/O device that the processor intends to access."},{"text":"The data bus.","correct":false,"explanation":"The data bus carries data and instructions between components, not the location being accessed. The processor specifies that location using the address bus."},{"text":"The control bus.","correct":false,"explanation":"The control bus carries command and timing signals, such as read, write and interrupt signals. The address bus identifies the memory location or I/O device."},{"text":"The expansion bus.","correct":false,"explanation":"An expansion bus connects peripheral hardware to the computer system; it does not specifically identify locations for processor access. That is the address bus’s role."}]},{"id":"f8d1f239-185b-455c-bcd2-f38712d79e16","cardType":"basic","points":1,"front":"Why is the data bus described as bidirectional?","back":"Data must travel both ways: from memory/IO to the processor (reading) and from the processor to memory/IO (writing).","mcqOptions":[{"text":"Data must travel both ways: from memory/IO to the processor (reading) and from the processor to memory/IO (writing).","correct":true,"explanation":"During a read, data travels to the processor; during a write, it travels away from the processor. Supporting these two directions makes the data bus bidirectional."},{"text":"Data travels only one way: from memory/IO to the processor (reading), but not from the processor to memory/IO (writing).","correct":false,"explanation":"This describes a one-way input bus and ignores write operations. The data bus is bidirectional because data travels to the processor when reading and away when writing."},{"text":"Data travels only one way: from the processor to memory/IO (writing), but not from memory/IO to the processor (reading).","correct":false,"explanation":"This describes a one-way output bus and ignores read operations. The data bus is bidirectional because it carries data in both directions for reads and writes."},{"text":"Data must travel simultaneously both ways: from memory/IO to the processor and from the processor to memory/IO at the same time.","correct":false,"explanation":"Bidirectional does not mean simultaneous transmission in both directions. It means the bus can carry data towards the processor during reads and away during writes."}]},{"id":"5a22b353-c972-45b3-95b1-8a65df0c6c03","cardType":"basic","points":3,"front":"State three types of signals carried by the control bus.","back":"

Read / Write signals
Clock (timing) pulses
Interrupt requests

","mcqOptions":[{"text":"

Read / Write signals
Clock (timing) pulses
Interrupt requests

","correct":true,"explanation":"The control bus coordinates system operations by carrying commands such as read and write, synchronising clock pulses, and requests that interrupt the processor’s current activity."},{"text":"

Memory address values
Data values
Instruction codes

","correct":false,"explanation":"This confuses the three system buses: addresses use the address bus, while data and instructions use the data bus. Control signals include read/write, clock and interrupt signals."},{"text":"

Read / Write signals
Memory address values
Data values

","correct":false,"explanation":"Only read/write signals belong on the control bus. Addresses use the address bus and data uses the data bus; clock pulses and interrupt requests are control signals."},{"text":"

Clock (timing) pulses
Interrupt requests
Instruction codes

","correct":false,"explanation":"Clock pulses and interrupt requests are control signals, but instruction codes travel on the data bus. Read/write signals provide the missing valid control-bus example."}]},{"id":"f9c042cf-6439-45de-b719-61e2d6f96156","cardType":"basic","points":3,"front":"Outline the steps for the processor to read a value from main memory.","back":"

Processor sends location via address bus.
Processor sends read signal via control bus.
Memory places value onto data bus for the processor.

","mcqOptions":[{"text":"

Processor sends location via address bus.
Processor sends read signal via control bus.
Memory places value onto data bus for the processor.

","correct":true,"explanation":"The address bus selects the location, the read signal tells memory which operation to perform, and memory returns the requested value along the data bus."},{"text":"

Processor sends location via data bus.
Processor sends read signal via control bus.
Memory places value onto data bus for the processor.

","correct":false,"explanation":"This incorrectly sends the location on the data bus. The processor must place the memory address on the address bus before issuing a read signal."},{"text":"

Processor sends location via address bus.
Processor sends write signal via control bus.
Memory places value onto data bus for the processor.

","correct":false,"explanation":"A write signal tells memory to store incoming data rather than return a value. Reading requires the processor to issue a read signal through the control bus."},{"text":"

Processor sends location via address bus.
Processor sends read signal via control bus.
Memory places value onto address bus for the processor.

","correct":false,"explanation":"The address bus identifies the requested location and does not carry its contents. After receiving the read signal, memory returns the value on the data bus."}]},{"id":"390d83e8-c102-4766-b35a-934e24bc99b7","cardType":"basic","points":1,"front":"If a computer has an $n$-bit address bus, how many unique memory locations can it address?","back":"$$2^n$ addresses.","mcqOptions":[{"text":"$$2^n$ addresses.","correct":true,"explanation":"Each of the $n$ address lines can be either 0 or 1, producing $2^n$ distinct binary combinations and therefore $2^n$ unique addresses."},{"text":"$$2n$ addresses.","correct":false,"explanation":"This multiplies the number of bits by two instead of counting binary combinations. With two possible states per bit, an $n$-bit bus provides $2^n$ addresses."},{"text":"$$n^2$ addresses.","correct":false,"explanation":"Squaring the bus width does not count its possible binary patterns. Since every bit independently has two states, the total number of addresses is $2^n$."},{"text":"$$2^{n-1}$ addresses.","correct":false,"explanation":"This incorrectly omits one address bit, halving the available address space. All $n$ bits contribute to the address, giving $2^n$ possible addresses."}]},{"id":"2cbd8228-841b-41f2-a8dc-58a5d63d29ce","cardType":"cloze","points":null,"front":"In a [ ] system, each unique address identifies one byte of data.","back":"In a byte-addressable system, each unique address identifies one byte of data.","mcqOptions":[{"text":"byte-addressable","correct":true,"explanation":"A byte-addressable system assigns a separate address to every byte, so each unique address identifies exactly one byte of stored data."},{"text":"word-addressable","correct":false,"explanation":"A word-addressable system assigns each address to a complete machine word rather than one byte. The system described is therefore byte-addressable."},{"text":"bit-addressable","correct":false,"explanation":"A bit-addressable system would assign each unique address to an individual bit, not a byte. One byte per address defines a byte-addressable system."},{"text":"block-addressable","correct":false,"explanation":"Block addressing identifies groups of bytes rather than one byte at each unique address. The stated one-byte mapping is specifically called byte-addressable."}]},{"id":"227a3442-5a76-4185-ab1f-efb97d79a55e","cardType":"cloze","points":null,"front":"In a byte-addressable system, each unique address identifies [ ] of data.","back":"In a byte-addressable system, each unique address identifies one byte of data.","mcqOptions":[{"text":"one byte","correct":true,"explanation":"Byte-addressable memory gives every byte its own unique address. A byte normally contains eight bits, but the address identifies the whole byte."},{"text":"one bit","correct":false,"explanation":"Assigning every address to one bit would describe bit-addressable memory. In a byte-addressable system, each unique address identifies one complete byte."},{"text":"one word","correct":false,"explanation":"Assigning every address to a processor word would describe word-addressable memory. Byte-addressable memory instead associates each unique address with one byte."},{"text":"one kilobyte","correct":false,"explanation":"A kilobyte is a large block containing many individually addressable bytes. In a byte-addressable system, each address identifies only one byte."}]},{"id":"b3dfc0ec-2a61-40de-845f-ea3a0a22fb75","cardType":"basic","points":1,"front":"What happens to the number of addressable locations if the address bus width increases by 1 bit?","back":"The number of addressable locations doubles.","mcqOptions":[{"text":"The number of addressable locations doubles.","correct":true,"explanation":"An $n$-bit address bus provides $2^n$ addresses. Adding one bit gives $2^{n+1}$, which is twice the original number of locations."},{"text":"The number of addressable locations quadruples.","correct":false,"explanation":"Quadrupling would require two additional address bits because $2^{n+2}=4\\times2^n$. Adding only one bit doubles the number of addressable locations."},{"text":"The number of addressable locations increases by one.","correct":false,"explanation":"This treats bus width and address count as if they increased linearly. One extra binary bit creates twice as many combinations, so the address count doubles."},{"text":"The number of addressable locations halves.","correct":false,"explanation":"Halving would result from removing one address bit, not adding one. Increasing the width by one bit doubles the number of possible binary addresses."}]},{"id":"4fc25b99-90fe-43f8-810a-d671e9a2fd18","cardType":"basic","points":2,"front":"Define von Neumann architecture.","back":"A design where instructions and data are stored in the same main memory and share the same buses.","mcqOptions":[{"text":"A design where instructions and data are stored in the same main memory and share the same buses.","correct":true,"explanation":"Von Neumann architecture uses one shared memory and shared communication buses for both program instructions and data, allowing both to be stored in the same address space."},{"text":"A design where instructions and data are stored in separate main memories and use separate buses.","correct":false,"explanation":"Separate memories and separate buses describe Harvard architecture, not von Neumann architecture. Von Neumann systems store instructions and data in the same main memory and transfer them over shared buses."},{"text":"A design where instructions and data are stored in the same main memory but use separate buses.","correct":false,"explanation":"The misconception is that memory can be shared while each content type has dedicated buses. Von Neumann architecture shares both main memory and buses between instructions and data."},{"text":"A design where instructions are stored in the processor while data uses the main memory.","correct":false,"explanation":"Storing instructions inside the processor is not the defining arrangement. In von Neumann architecture, instructions and data reside together in the same main memory and share the same buses."}]},{"id":"a83bd414-fd94-4030-86ac-728736df6f8e","cardType":"basic","points":2,"front":"What is the von Neumann bottleneck?","back":"A delay where the processor waits because instructions and data cannot be transferred simultaneously over the shared bus.","mcqOptions":[{"text":"A delay where the processor waits because instructions and data cannot be transferred simultaneously over the shared bus.","correct":true,"explanation":"Instructions and data use the same bus in von Neumann architecture, so only one can be transferred at a time and the processor may have to wait."},{"text":"A delay where the processor waits because instructions and data are transferred simultaneously over the shared bus.","correct":false,"explanation":"Simultaneous transfer would reduce the bottleneck rather than cause it. The delay occurs because instructions and data cannot be transferred simultaneously over the shared bus."},{"text":"A delay where the processor waits because arithmetic operations cannot be performed simultaneously by the shared ALU.","correct":false,"explanation":"The von Neumann bottleneck concerns competition for a shared bus, not arithmetic speed. The processor waits because instruction and data transfers cannot occur simultaneously over that bus."},{"text":"A delay where the processor waits because instructions and data use separate transfer buses between separate memories.","correct":false,"explanation":"Separate buses are a feature of Harvard architecture and permit simultaneous transfers. The von Neumann bottleneck arises from instructions and data having to share one bus."}]},{"id":"56ea3385-1e4e-491a-abb0-52947e760971","cardType":"basic","points":2,"front":"Define Harvard architecture.","back":"A design where instructions and data are stored in separate memories with separate buses for each.","mcqOptions":[{"text":"A design where instructions and data are stored in separate memories with separate buses for each.","correct":true,"explanation":"Harvard architecture provides independent storage and communication paths for instructions and data, enabling the processor to access both at the same time."},{"text":"A design where instructions and data are stored in the same memory with shared buses for each.","correct":false,"explanation":"Shared memory and shared buses define von Neumann architecture. Harvard architecture instead keeps instructions and data in separate memories and provides a separate bus for each."},{"text":"A design where instructions and data are stored in separate memories with shared buses for each.","correct":false,"explanation":"Separate memories alone do not give the defining independent access paths if the bus remains shared. Harvard architecture uses both separate memories and separate buses."},{"text":"A design where instructions and data are stored in the same memory with separate buses for each.","correct":false,"explanation":"Keeping instructions together with data is characteristic of von Neumann storage, even if multiple buses are suggested. Harvard architecture separates both the memories and their buses."}]},{"id":"4e885966-9ab2-4364-a102-ce6df4ba34eb","cardType":"cloze","points":null,"front":"Von Neumann architecture is typically used in [ ], while Harvard architecture is used in embedded systems (e.g. DSP).","back":"Von Neumann architecture is typically used in general-purpose computers, while Harvard architecture is used in embedded systems (e.g. DSP).","mcqOptions":[{"text":"general-purpose computers","correct":true,"explanation":"General-purpose computers commonly follow the von Neumann model because programs and data share a single memory system, providing flexibility for running many different applications."},{"text":"digital signal processors","correct":false,"explanation":"Digital signal processors commonly use Harvard architecture so that instructions and signal data can be accessed simultaneously. The expected von Neumann application is general-purpose computers."},{"text":"real-time embedded systems","correct":false,"explanation":"Real-time embedded systems often favour Harvard architecture because separate instruction and data paths support predictable, simultaneous access. Von Neumann architecture is typically associated with general-purpose computers."},{"text":"dedicated control systems","correct":false,"explanation":"Dedicated control systems are embedded applications and commonly benefit from Harvard-style separation of instructions and data. General-purpose computers are the typical use named for von Neumann architecture."}]},{"id":"c7b0da0b-b4cb-464b-b960-7be1ebe60c99","cardType":"cloze","points":null,"front":"Von Neumann architecture is typically used in general-purpose computers, while Harvard architecture is used in [ ] (e.g. DSP).","back":"Von Neumann architecture is typically used in general-purpose computers, while Harvard architecture is used in embedded systems (e.g. DSP).","mcqOptions":[{"text":"embedded systems","correct":true,"explanation":"Embedded systems, including many digital signal processors, commonly use Harvard architecture because separate instruction and data paths support simultaneous access and predictable real-time performance."},{"text":"general-purpose computers","correct":false,"explanation":"General-purpose computers are typically associated with von Neumann architecture, where programs and data share memory. Harvard architecture is commonly used in embedded systems such as DSP devices."},{"text":"desktop workstations","correct":false,"explanation":"Desktop workstations are general-purpose machines and are therefore usually described using the von Neumann model. Harvard architecture is typically associated with embedded systems and DSP applications."},{"text":"conventional personal computers","correct":false,"explanation":"Conventional personal computers are general-purpose systems commonly modelled using von Neumann architecture. The expected application of Harvard architecture is embedded systems, particularly those with real-time requirements."}]},{"id":"fb22a6e9-6f5c-40af-be64-56ac259c55bb","cardType":"basic","points":2,"front":"Why is Harvard architecture advantageous for Digital Signal Processing (DSP)?","back":"It allows the processor to fetch the next instruction while simultaneously reading or writing data, meeting strict real-time timing requirements.","mcqOptions":[{"text":"It allows the processor to fetch the next instruction while simultaneously reading or writing data, meeting strict real-time timing requirements.","correct":true,"explanation":"Separate instruction and data buses permit both accesses during the same cycle, increasing throughput and helping a DSP complete repeated signal-processing operations within strict deadlines."},{"text":"It forces the processor to fetch each instruction before separately reading or writing data, meeting strict real-time timing requirements.","correct":false,"explanation":"Alternating the two accesses describes the limitation of a shared bus and does not exploit Harvard architecture. Separate buses allow an instruction fetch and data access simultaneously."},{"text":"It allows the processor to avoid fetching instructions by permanently storing them in registers, meeting strict real-time timing requirements.","correct":false,"explanation":"Harvard architecture does not avoid instruction fetching or keep every instruction in registers. Its advantage is simultaneous instruction fetching and data reading or writing through separate buses."},{"text":"It allows the processor to share a single bus while sequentially reading or writing data, meeting strict real-time timing requirements.","correct":false,"explanation":"Using one shared path would create bus contention and undermine real-time performance. Harvard architecture instead uses separate paths to fetch instructions while accessing data simultaneously."}]},{"id":"c6f5fd44-680e-4706-bf75-705266a9e9ba","cardType":"basic","points":1,"front":"Within the processor, which component is responsible for coordinating movements and sending signals to other parts?","back":"The control unit.","mcqOptions":[{"text":"The control unit.","correct":true,"explanation":"The control unit coordinates processor activity by decoding instructions and issuing control signals that direct data movement and the actions of other components."},{"text":"The arithmetic logic unit.","correct":false,"explanation":"The arithmetic logic unit performs calculations and logical comparisons rather than coordinating all processor components. The control unit sends the signals that direct movements and operations."},{"text":"The cache memory.","correct":false,"explanation":"The cache stores frequently needed instructions and data to reduce access time, but it does not coordinate processor activity. That signalling role belongs to the control unit."},{"text":"The system clock.","correct":false,"explanation":"The clock supplies regular timing pulses but does not determine which movements and operations occur. The control unit coordinates them by sending control signals to other components."}]},{"id":"94cd8c18-6c69-4a8a-b466-b5ab6c323d49","cardType":"basic","points":1,"front":"Identify two types of operations performed by the ALU.","back":"

Arithmetic (e.g. addition, subtraction)
Logical (e.g. AND, OR, NOT)

","mcqOptions":[{"text":"

Arithmetic (e.g. addition, subtraction)
Logical (e.g. AND, OR, NOT)

","correct":true,"explanation":"The ALU carries out numerical arithmetic and Boolean logical operations. Addition and subtraction are arithmetic examples, while AND, OR and NOT are logical examples."},{"text":"

Input (e.g. keyboard, microphone)
Output (e.g. monitor, printer)

","correct":false,"explanation":"Input and output operations transfer data between the computer and peripherals; they are not the ALU’s two main operation types. The correct categories are arithmetic and logical operations."},{"text":"

Fetching (e.g. address, instruction)
Decoding (e.g. opcode, operand)

","correct":false,"explanation":"Fetching and decoding are stages coordinated by the control unit, not operation categories performed by the ALU. The ALU performs arithmetic and logical operations."},{"text":"

Primary storage (e.g. RAM, cache)
Secondary storage (e.g. SSD, HDD)

","correct":false,"explanation":"Primary and secondary storage describe ways of retaining data rather than processing it. The ALU’s relevant operation types are arithmetic calculations and logical Boolean operations."}]}]}],"examCountdown":{"examDate":"2027-06-07","paperLabel":"Paper 1"},"heading":"Internal hardware components of a computer","title":"Internal hardware components of a computer Flashcards","topbar":{"backHref":"/a-level/computer-science/aqa/flashcards"},"topicSidebar":"$L38"}]}],"topicId":"d1965561-a9fb-5899-9429-6e09621a2e1f","walled":"$L39"}],"$L3a","$L3b"]